Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/26/2024 and 5/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamei (WO 2019176454 A1).
Regarding claim 1, Kamei discloses a light detection apparatus (Fig. 10), comprising:
a sensor substrate (30) that includes a first semiconductor substrate (32; pg. 9 of translation: “semiconductor substrate”) on which a plurality of photoelectric converters (FD; pg. 9: “photodiode”) is arranged; and
a logic substrate (1) that includes
a second semiconductor substrate (12; pg. 3: “semiconductor substrate”) to which a logic circuit (pg. 10: “part of a signal processing circuit”) is provided, and
a first wiring layer (See annotated figure) that is stacked (stacked in the Z direction) on the second semiconductor substrate,
the sensor substrate and the logic substrate being arranged in a layered formation (layered in the Z direction) such that the first wiring layer of the logic substrate faces (faces towards) the sensor substrate, wherein
a second wiring layer (See annotated figure) that includes wiring (16) and an insulator (15) is formed inside of the second semiconductor substrate, the wiring extending in parallel (parallel along the X direction) with a first surface (See annotated figure for surface designation) that is a surface of the second semiconductor substrate that is situated on a side of the first wiring layer, the insulator insulating the wiring from the second semiconductor substrate (completely insulating), and
the wiring in the second wiring layer is electrically connected to a specified portion of a connection target (13) formed in the first surface of the second semiconductor substrate (at least a portion of target 13 is within substrate 12) or a second surface of the second semiconductor substrate (See annotated figure for surface designation, annotated as 1S) that is situated opposite to the first surface (opposite in the Z direction).
Illustrated below is a marked and annotated figure of Fig. 10 of Kamei.
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Regarding claim 2, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein the wiring in the second wiring layer has a larger cross-sectional area (See annotated figure for area annotations) in a width direction (X direction) than wiring situated in the first wiring layer (See annotated figure for area annotations).
Regarding claim 3, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein the wiring in the second wiring layer is power supply wiring that applies a power supply voltage to the connection target (pg. 3 describes the target 13 as “a transistor”, and this wiring is shown connected to a source/drain terminal of the transistor. Thus, this wiring is configured to supply at least some power at some voltage to this target.).
Regarding claim 4, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein the wiring in the second wiring layer is electrically connected to the specified portion through a connection conductor (14-1, See annotated figure; alternatively this conductor is designated as 14-1 with 14-W) that extends in parallel with a direction (Z direction) of a thickness of the second semiconductor substrate.
Regarding claim 5, Kamei discloses the light detection apparatus according to claim 4 (Fig. 10), wherein
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor (14-1, See annotated figure), wiring (14-W, See annotated figure) situated in the first wiring layer, and a second connection conductor (14-2, an encircled portion of 16 within 11, See annotated figure), the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the first wiring layer from the wiring in the second wiring layer (this is the above-selected conductor in the figure), the second connection conductor extending in parallel with the thickness direction toward the specified portion from the wiring in the first wiring layer (this is the above-selected conductor in the figure), or
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor, wiring situated in a third wiring layer that is formed on the second surface, and a second connection conductor, the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the third wiring layer from the wiring in the second wiring layer, the second connection conductor extending in parallel with the thickness direction toward the specified portion from the wiring in the third wiring layer.
Regarding claim 6, Kamei discloses the light detection apparatus according to claim 4 (Fig. 10), wherein the wiring in the second wiring layer is directly electrically connected to the specified portion only through the connection conductor (selecting the alternative interpretation 14-1 with 14-W) extending in parallel with the direction of the thickness of the second semiconductor substrate toward the specified portion situated in the second semiconductor substrate from the wiring in the second wiring layer (each of the portions 14-1 and 14-W have some thickness extending in the Z direction).
Regarding claim 7, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein the second wiring layer is a multilayered wiring layer (layers 16-1 and 16-2, 12; See annotated figure) in which the pieces of wiring (pieces 16-1/16-2) of a plurality of the pieces of wiring are spaced in a layered formation (layered upon 15, which is layered upon 12; layered upon a portion of 14) in the direction (Z direction) of the thickness of the second semiconductor substrate, and the piece of wiring in an upper layer and the piece of wiring in a lower layer are connected to each other through a via (16-V).
Regarding claim 8, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein a material of the insulator is at least one of silicon oxide (pg. 3: “such as SiO2 or SiN”), silicon nitride, silicon oxynitride, or carbon-containing silicon oxide.
Regarding claim 9, Kamei discloses the light detection apparatus according to claim 1 (Fig. 10), wherein a material of the wiring is at least one of tungsten, copper (pg. 3: “a highly conductive metal such as Cu”), titanium, tantalum, cobalt, or aluminum.
Regarding independent claim 10, Kamei discloses an electronic apparatus (Fig. 10), comprising
a light detection apparatus (pg. 10: “imaging apparatus”) that includes
a sensor substrate (30) that includes a first semiconductor substrate (32; pg. 9 of translation: “semiconductor substrate”) on which a plurality of photoelectric converters (FD; pg. 9: “photodiode”) is arranged, and
a logic substrate (1) that includes
a second semiconductor substrate (12; pg. 3: “semiconductor substrate”) to which a logic circuit (pg. 10: “part of a signal processing circuit”) is provided, and
a first wiring layer (See annotated figure) that is stacked (stacked in the Z direction) on the second semiconductor substrate,
the sensor substrate and the logic substrate being arranged in a layered formation (layered in the Z direction) such that the first wiring layer of the logic substrate faces (faces towards) the sensor substrate, wherein
a second wiring layer (See annotated figure) that includes wiring (16) and an insulator (15) is formed inside of the second semiconductor substrate, the wiring extending in parallel (parallel along the X direction) with a first surface (See annotated figure for surface designation) that is a surface of the second semiconductor substrate that is situated on a side of the first wiring layer, the insulator insulating the wiring from the second semiconductor substrate (completely insulating), and
the wiring in the second wiring layer is electrically connected to a specified portion of a connection target (13) formed in the first surface of the second semiconductor substrate (at least a portion of target 13 is within substrate 12) or a second surface of the second semiconductor substrate (See annotated figure for surface designation, annotated as 1S) that is situated opposite to the first surface (opposite in the Z direction).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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