DETAILED ACTION
This office action is in response to applicant’s amendments filed on 08/25/2026.
Currently claims 1-12, 14-16, 18, 21-22 and 24-25 are pending in the application.
Response to Arguments
Applicant's arguments filed 08/25/2026 with respect to independent claims 1, 6 and 14 have been fully considered but they are not persuasive.
Item #1:
Issue raised - Applicant argues that Long involves planar transistors whose gates are distributed parallel to the substrate rather than in a vertically stacked structure, and therefore fails to teach the laminated first and second gates (Remarks, p. 11).
Applicable Rule - The factual inquiries set forth in Graham v. John Deere Co.
Analysis – Applicant’s argument is not persuasive. Long is not relied upon for the laminated gates; Long is relied upon for the gate insulating layer (GD1) proximal to the source region (14) having a greater dielectric constant than the gate insulating layer (GD2) proximal to the drain region (16). The laminated first and second gates are taught by Oh. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, Long's dielectric profile is defined along the source-to-drain direction of the channel; applying it to Xu's vertical pillar, in which the source-to-drain direction is perpendicular to the substrate, simply places the higher-dielectric-constant portion adjacent the source region (107).
Conclusion – Combination of Xu, Long and Oh teaches the limitation.
Item #2:
Issue raised - Applicant argues that Oh “does not involve the gate including a first gate proximal to the drain region and a second gate proximal to the source region that are laminated and the second gate having a greater work function than the first gate” and “cannot provide teaching on how to achieve vertical non-uniform distribution through a vertically stacked gate structure in a vertical transistor.”
Applicable Rule - The factual inquiries set forth in Graham v. John Deere Co.
Analysis – The examiner respectfully disagrees. Oh discloses a vertical transistor in which a pillar (110) has a source (S) at its lower portion and a drain (D) at its upper portion, and the gate (130) includes a first gate (130a) surrounding the channel region and a second gate (130b) positioned over the first gate (130a) at the drain (D) (Fig. 7; [0059] - [0061]). The second gate (130b) has a second work function less than the first work function of the first gate (130a) (Fig. 8; [0061]). Thus, Oh's gates (130b, 130a) are stacked along the height of the pillar (i.e., laminated), the lower-work-function gate (130b) is proximal to the drain (D), and the higher-work-function gate (130a) is proximal to the source (S). Applicant itself characterizes Oh as providing “a low-work-function gate on the drain side” (Remarks, p. 12). Oh therefore teaches the amended limitation in a vertical transistor; Applicant's planar-transistor distinction of Long does not apply to Oh.
Conclusion – Combination of Xu, Long and Oh teaches the limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0103424 A1 (Xu) in view of US 6,225,669 B1 (Long) and further in view of US 2016/0300886 A1 (Oh).
Regarding claim 1, Xu discloses, a memory cell, comprising: a vertical transistor (100; Fig. 1; vertical transistor; [0026]) comprising:
a semiconductor pillar (102; Fig. 1; silicon pillar; [0026]) extending in a direction perpendicular to a substrate (101) and comprising a drain region (106), a channel region (as annotated on Fig. 4g), and a source region (107) disposed sequentially (as annotated on Fig. 4g); and
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a gate insulating layer (207; Fig. 4g; gate dielectric layer; [0026]) and a gate (208; Fig. 4g; gate/word line; [0033]), the gate (208) and at least a portion of the gate insulating layer (207) being disposed sequentially around the channel region of the semiconductor pillar (102),
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wherein the drain region (106) is configured to be electrically connected to a bitline (202; Fig. 4g; bit line; [0036]), and the source region (107) is configured to be electrically connected to a capacitor structure (206; Fig. 2; capacitor; [0029]).
But Xu fails to teach explicitly, wherein the vertical transistor includes at least one of the gate insulating layer proximal to the source region having a greater dielectric constant than the gate insulating layer proximal to the drain region, and the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Long discloses, wherein the transistor (30; transistor; Fig. 2 and 3c; col. 2, lines 1-10) includes at least one of the gate insulating layer (GD1) proximal to the source region (14) having a greater dielectric constant than the gate insulating layer (GD2) proximal to the drain region (16) (Fig. 2 and 3c; col. 5, lines 25-40).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu and Long before him/her, to form the gate insulating layer (207) of the vertical transistor (100) of Xu with the gate insulating layer proximal to the source region (107) having a greater dielectric constant than the gate insulating layer proximal to the drain region (106) as taught by Long, (1) because gate leakage current can be reduced by engineering the gate dielectric layer along the channel (Long, col. 1, lines 18-35), which improves charge retention of Xu's capacitor-based memory cell; (2) since the modification amounts to the use of a known technique (Long's source-side higher-dielectric-constant gate insulator) to improve a similar device in the same way (MPEP 2143(I)(C)), the source-to-drain direction of Xu's pillar merely being perpendicular rather than parallel to the substrate; and (3) with a reasonable expectation of success, yielding the predictable result of a memory cell having a gate insulating layer with a higher dielectric constant adjacent the source region and reduced leakage. Absent this teaching in Xu, a person with ordinary skill in the art would be motivated to reach out to Long while forming a memory cell of Xu.
But the combination of Xu and Long fails to teach explicitly, wherein the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Oh discloses, a vertical transistor (Fig. 7; [0057] – [0060]) comprising a semiconductor pillar (110; pillar; Fig. 7; [0057]) having a drain region (D) and a source region (S), and a gate (130; gate; Fig. 7; [0060]), wherein the gate (130) comprises a first gate (130b; second gate; Fig. 7; [0060]) proximal to the drain region (D) and a second gate (130a; first gate; Fig. 7; [0060]) proximal to the source region (S) that are laminated (130b is positioned over 130a along the height of the pillar 110; Fig. 7; [0059] - [0060]), the second gate (130a) having a greater work function than the first gate (130b) (130a has a first work function greater than the second work function of 130b; Fig. 8; [0061]).
Note: Oh's second gate (130b) and first gate (130a) are mapped to the claimed “first gate” and “second gate,” respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu, Long and Oh before him/her, to form the gate (208) of the vertical transistor (100) of the combination of Xu and Long as the laminated first gate (130b) and second gate (130a) of Oh, with the lower-work-function gate proximal to the drain region (106) and the higher-work-function gate proximal to the source region (107), (1) because lowering the work function of the gate portion adjacent the drain narrows the work-function difference at the drain-side electric-field concentration region and thereby reduces gate-induced drain leakage (Oh, Fig. 8; [0061]), complementing the leakage reduction of Long's gate insulating layer; (2) since the modification amounts to a simple substitution of one known vertical-transistor gate (Oh's stacked dual-work-function gate 130a/130b) for another (Xu's single gate 208) (MPEP 2143(I)(B)), and placing the lower-work-function gate at the bottom of Xu's pillar, where Xu's drain (106) is located, rather than at the top as in Oh, is a mere reversal of the stacking order (MPEP 2144.04(VI)(A)); and (3) with a reasonable expectation of success, because Xu and Oh are both directed to vertical pillar transistors with a gate surrounding the channel region and used as memory-cell selection devices, yielding the predictable result of a memory cell having reduced drain-side leakage. Absent this teaching in Xu and Long, a person with ordinary skill in the art would be motivated to reach out to Oh while forming a memory cell of Xu and Long.
Regarding claim 2, the combination of Xu, Long and Oh teaches, the memory cell according to claim 1, wherein Oh teaches the gate insulating layer (120; gate insulating layer; Fig. 7; [0060]-[0061]) is disposed around the drain region (D), the channel region (as annotated in Fig. 7), and the source region (S) (Fig. 7; [0060]-[0061]).
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Regarding claim 5, the combination of Xu, Long and Oh teaches, the memory cell according to claim 1, wherein Xu teaches dopant ions in the source region, dopant ions in the drain region, and dopant ions in the channel region are of a same polarity (as annotated on Fig. 4g, drain, source and channel are made of same pillar material, therefore must be of same polarity).
Claims 6-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0103424 A1 (Xu) in view of US 6,225,669 B1 (Long) and further in view of US 2016/0300886 A1 (Oh).
Regarding claim 6, Xu discloses, a memory, comprising:
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a plurality of wordlines (208; Figs. 1 and 4g; gate/word line; [0026]), and memory cells (memory consists of plurality of memory cells) disposed in an array (as evident in Figs. 1 and 2),
each of the memory cells comprising a vertical transistor (100; Fig. 1; vertical transistor; [0026]),
wherein the vertical transistor (100) comprising:
a semiconductor pillar (102; Fig. 1; silicon pillar; [0026]) extending in a direction perpendicular to a substrate (101) and comprising a drain region (106), a channel region (as annotated on Fig. 4g), and a source region (107) disposed sequentially (as annotated on Fig. 4g); and
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a gate insulating layer (207; Fig. 4g; gate dielectric layer; [0026]) and a gate (208; Fig. 4g; gate/word line; [0033]), the gate (208) and at least a portion of the gate insulating layer (207) being disposed sequentially around the channel region of the semiconductor pillar (102),
wherein the drain region (106) is configured to be electrically connected to a bitline (202; Fig. 4g; bit line; [0036]), and the source region (107) is configured to be electrically connected to a capacitor structure (206; Fig. 2; capacitor; [0029]);
wherein each of the wordlines (208) is electrically connected to the gates ([0033]) of the memory cells arranged in a same row in a first direction (horizontal; Fig. 4g), the first direction being parallel to the substrate (101; Fig. 4g).
But Xu fails to teach explicitly, wherein the vertical transistor includes at least one of the gate insulating layer proximal to the source region having a greater dielectric constant than the gate insulating layer proximal to the drain region, and the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Long discloses, wherein the transistor (30; transistor; Fig. 2 and 3c; col. 2, lines 1-10) includes at least one of the gate insulating layer (GD1) proximal to the source region (14) having a greater dielectric constant than the gate insulating layer (GD2) proximal to the drain region (16) (Fig. 2 and 3c; col. 5, lines 25-40).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu and Long before him/her, to form the gate insulating layer (207) of the vertical transistor (100) of Xu with the gate insulating layer proximal to the source region (107) having a greater dielectric constant than the gate insulating layer proximal to the drain region (106) as taught by Long, (1) because gate leakage current can be reduced by engineering the gate dielectric layer along the channel (Long, col. 1, lines 18-35), which improves charge retention of Xu's capacitor-based memory cell; (2) since the modification amounts to the use of a known technique (Long's source-side higher-dielectric-constant gate insulator) to improve a similar device in the same way (MPEP 2143(I)(C)), the source-to-drain direction of Xu's pillar merely being perpendicular rather than parallel to the substrate; and (3) with a reasonable expectation of success, yielding the predictable result of a memory having a gate insulating layer with a higher dielectric constant adjacent the source region and reduced leakage. Absent this teaching in Xu, a person with ordinary skill in the art would be motivated to reach out to Long while forming a memory of Xu.
But the combination of Xu and Long fails to teach explicitly, wherein the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Oh discloses, a vertical transistor (Fig. 7; [0057] – [0060]) comprising a semiconductor pillar (110; pillar; Fig. 7; [0057]) having a drain region (D) and a source region (S), and a gate (130; gate; Fig. 7; [0060]), wherein the gate (130) comprises a first gate (130b; second gate; Fig. 7; [0060]) proximal to the drain region (D) and a second gate (130a; first gate; Fig. 7; [0060]) proximal to the source region (S) that are laminated (130b is positioned over 130a along the height of the pillar 110; Fig. 7; [0059] - [0060]), the second gate (130a) having a greater work function than the first gate (130b) (130a has a first work function greater than the second work function of 130b; Fig. 8; [0061]).
Note: Oh's second gate (130b) and first gate (130a) are mapped to the claimed “first gate” and “second gate,” respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu, Long and Oh before him/her, to form the gate (208) of the vertical transistor (100) of the combination of Xu and Long as the laminated first gate (130b) and second gate (130a) of Oh, with the lower-work-function gate proximal to the drain region (106) and the higher-work-function gate proximal to the source region (107), (1) because lowering the work function of the gate portion adjacent the drain narrows the work-function difference at the drain-side electric-field concentration region and thereby reduces gate-induced drain leakage (Oh, Fig. 8; [0061]), complementing the leakage reduction of Long's gate insulating layer; (2) since the modification amounts to a simple substitution of one known vertical-transistor gate (Oh's stacked dual-work-function gate 130a/130b) for another (Xu's single gate 208) (MPEP 2143(I)(B)), and placing the lower-work-function gate at the bottom of Xu's pillar, where Xu's drain (106) is located, rather than at the top as in Oh, is a mere reversal of the stacking order (MPEP 2144.04(VI)(A)); and (3) with a reasonable expectation of success, because Xu and Oh are both directed to vertical pillar transistors with a gate surrounding the channel region and used as memory-cell selection devices, yielding the predictable result of a memory cell having reduced drain-side leakage. Absent this teaching in Xu and Long, a person with ordinary skill in the art would be motivated to reach out to Oh while forming a memory cell of Xu and Long.
Regarding claim 7, the combination of Xu, Long and Oh teaches, the memory according to claim 6, wherein Oh teaches the gate insulating layer (120; gate insulating layer; Fig. 7; [0060]-[0061]) is disposed around the drain region (D), the channel region (as annotated in Fig. 7), and the source region (S) (Fig. 7; [0060]-[0061]).
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Regarding claim 12, the combination of Xu, Long and Oh teaches, the memory according to claim 6, wherein Xu teaches dopant ions of the source region, dopant ions of the drain region, and dopant ions of the channel region are of a same polarity (as annotated on Fig. 4g, drain, source and channel are made of same pillar material, therefore must be of same polarity).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0103424 A1 (Xu) in view of US 6,225,669 B1 (Long) and further in view of US 2016/0300886 A1 (Oh).
Regarding claim 14, Xu discloses, a method for manufacturing a memory, comprising:
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forming, at a side of a substrate (101; substrate; Fig. 1; [0028]), a semiconductor pillar (102; Fig. 1; silicon pillar; [0026]) extending in a direction perpendicular to a substrate (101) arranged in an array (as evident in Figs. 1 and 2) extending in a direction perpendicular to a substrate (101) and comprising a drain region (106), a channel region (as annotated on Fig. 4g), and a source region (107) disposed sequentially (as annotated on Fig. 4g); and
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forming a plurality of gates (part of 208 close to gate insulator layer; Fig. 4g; gate/word line; [0033]) and a plurality of wordlines (part of 208 away from gate insulator layer and connected to external components; Fig. 4g; gate/word line; [0033]), such that the gates and the wordlines are disposed sequentially around the channel regions (as annotated on Fig. 4g) of the semiconductor pillars (102) and the gates are insulated (gate insulating layer in between) from the semiconductor pillars (102); and
Note: The examiner would use layer 208 as ‘gate’ although it has two designated components, i.e., gate and word line, based on their physical locations with respect to gate insulating layer.
forming a gate insulating layer (207; Fig. 4g; gate dielectric layer; [0026]) and a gate (208; Fig. 4g; gate/word line; [0033]), the gate (208) and at least a portion of the gate insulating layer (207) being disposed around the channel region of the semiconductor pillar (102) and disposed between the semiconductor pillar (102) and the gate (208; Fig. 4g; gate/word line; [0033]),
wherein the drain region (106) is configured to be electrically connected to a bitline (202; Fig. 4g; bit line; [0036]), and the source region (107) is configured to be electrically connected to a capacitor structure (206; Fig. 2; capacitor; [0029]).
But Xu fails to teach explicitly, wherein the vertical transistor includes at least one of the gate insulating layer proximal to the source region having a greater dielectric constant than the gate insulating layer proximal to the drain region, and the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Long discloses, wherein the transistor (30; transistor; Fig. 2 and 3c; col. 2, lines 1-10) includes at least one of the gate insulating layer (GD1) proximal to the source region (14) having a greater dielectric constant than the gate insulating layer (GD2) proximal to the drain region (16) (Fig. 2 and 3c; col. 5, lines 25-40).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu and Long before him/her, to form the gate insulating layer (207) of the vertical transistor (100) of Xu with the gate insulating layer proximal to the source region (107) having a greater dielectric constant than the gate insulating layer proximal to the drain region (106) as taught by Long, (1) because gate leakage current can be reduced by engineering the gate dielectric layer along the channel (Long, col. 1, lines 18-35), which improves charge retention of Xu's capacitor-based memory cell; (2) since the modification amounts to the use of a known technique (Long's source-side higher-dielectric-constant gate insulator) to improve a similar device in the same way (MPEP 2143(I)(C)), the source-to-drain direction of Xu's pillar merely being perpendicular rather than parallel to the substrate; and (3) with a reasonable expectation of success, yielding the predictable result of a memory having a gate insulating layer with a higher dielectric constant adjacent the source region and reduced leakage. Absent this teaching in Xu, a person with ordinary skill in the art would be motivated to reach out to Long while forming a memory of Xu.
But the combination of Xu and Long fails to teach explicitly, wherein the gate comprises a first gate proximal to the drain region and a second gate proximal to the source region that are laminated, the second gate having a greater work function than the first gate.
However, in analogous art, Oh discloses, a vertical transistor (Fig. 7; [0057] – [0060]) comprising a semiconductor pillar (110; pillar; Fig. 7; [0057]) having a drain region (D) and a source region (S), and a gate (130; gate; Fig. 7; [0060]), wherein the gate (130) comprises a first gate (130b; second gate; Fig. 7; [0060]) proximal to the drain region (D) and a second gate (130a; first gate; Fig. 7; [0060]) proximal to the source region (S) that are laminated (130b is positioned over 130a along the height of the pillar 110; Fig. 7; [0059] - [0060]), the second gate (130a) having a greater work function than the first gate (130b) (130a has a first work function greater than the second work function of 130b; Fig. 8; [0061]).
Note: Oh's second gate (130b) and first gate (130a) are mapped to the claimed “first gate” and “second gate,” respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xu, Long and Oh before him/her, to form the gate (208) of the vertical transistor (100) of the combination of Xu and Long as the laminated first gate (130b) and second gate (130a) of Oh, with the lower-work-function gate proximal to the drain region (106) and the higher-work-function gate proximal to the source region (107), (1) because lowering the work function of the gate portion adjacent the drain narrows the work-function difference at the drain-side electric-field concentration region and thereby reduces gate-induced drain leakage (Oh, Fig. 8; [0061]), complementing the leakage reduction of Long's gate insulating layer; (2) since the modification amounts to a simple substitution of one known vertical-transistor gate (Oh's stacked dual-work-function gate 130a/130b) for another (Xu's single gate 208) (MPEP 2143(I)(B)), and placing the lower-work-function gate at the bottom of Xu's pillar, where Xu's drain (106) is located, rather than at the top as in Oh, is a mere reversal of the stacking order (MPEP 2144.04(VI)(A)); and (3) with a reasonable expectation of success, because Xu and Oh are both directed to vertical pillar transistors with a gate surrounding the channel region and used as memory-cell selection devices, yielding the predictable result of a memory cell having reduced drain-side leakage. Absent this teaching in Xu and Long, a person with ordinary skill in the art would be motivated to reach out to Oh while forming a memory cell of Xu and Long.
Allowable Subject Matter
Claims 3-4, 8-11, 15-16, 18, 21-22 and 24-25 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 3, the closest prior art, US 2023/0103424 A1 (Xu), in conjunction with US 6,225,669 B1 (Long) and US 2016/0300886 A1 (Oh), and in combination with the other claimed features, fails to disclose, “the memory cell according to claim 1, a work function difference between the second gate and the first gate being no less than 0.1 electron volt and no more than 0.5 electron volt”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the memory cell according to claim 1, a work function difference between the second gate and the first gate being no less than 0.1 electron volt and no more than 0.5 electron volt,’ is material to the inventive concept of the application at hand to reduce induced leakage while preserving or improving on/off performance.
Regarding claim 8, the closest prior art, US 2023/0103424 A1 (Xu), in conjunction with US 6,225,669 B1 (Long) and US 2016/0300886 A1 (Oh), and in combination with the other claimed features, fails to disclose, “each of the wordlines comprises a first wordline and a second wordline that are laminated, the first wordline is electrically connected to the first gate, the second wordline is electrically connected to the second gate, the second wordline is proximal to the source region, the first wordline is proximal to the drain region, and the second wordline has a greater work function than the first wordline”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the memory according to claim 6, each of the wordlines comprises a first wordline and a second wordline that are laminated, the first wordline is electrically connected to the first gate, the second wordline is electrically connected to the second gate, the second wordline is proximal to the source region, the first wordline is proximal to the drain region, and the second wordline has a greater work function than the first wordline,’ is material to the inventive concept of the application at hand to reduce induced leakage while preserving or improving on/off performance.
Regarding claim 10, the closest prior art, US 2023/0103424 A1 (Xu), in conjunction with US 6,225,669 B1 (Long) and US 2016/0300886 A1 (Oh), and in combination with the other claimed features, fails to disclose, “the memory according to claim 6, further comprising a plurality of bitlines extending in a second direction, wherein each of the bitlines is disposed at a side proximal to the substrate of the semiconductor pillars arranged in a same column in the second direction, the second direction being parallel to the substrate and having a designed angle with respect to the first direction”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the memory according to claim 6, further comprising a plurality of bitlines extending in a second direction, wherein each of the bitlines is disposed at a side proximal to the substrate of the semiconductor pillars arranged in a same column in the second direction, the second direction being parallel to the substrate and having a designed angle with respect to the first direction,’ is material to the inventive concept of the application at hand to reduce induced leakage while preserving or improving on/off performance.
Regarding claim 15, the closest prior art, US 2023/0103424 A1 (Xu), in conjunction with US 6,225,669 B1 (Long) and US 2016/0300886 A1 (Oh), and in combination with the other claimed features, fails to disclose, “the method according to claim 14, wherein prior to forming, at the side of the substrate, the semiconductor pillars arranged in the array and extending in the direction perpendicular to the substrate, the method further comprises: forming, at the side of the substrate, a plurality of bitlines spaced from each other in a first direction and extending in a second direction, the first direction having a designed angle with respect to the second direction, and the first direction and the second direction both being parallel to the substrate; and forming, at the side of the substrate, the semiconductor pillars arranged in the array and extending in the direction perpendicular to the substrate comprises: forming, at a side of the bitlines distal to the substrate, a first dielectric layer, a metal layer, and a second dielectric layer stacked together, patterning the second dielectric layer, the metal layer, and the first dielectric layer to obtain a metal structure and first holes arranged in an array, such that side surfaces of the metal structure and upper surfaces of the bitlines are exposed in the first holes; and forming sacrificial dielectric layers on side walls of the first holes, and epitaxially forming the semiconductor pillars up the first holes at the side of the bitlines distal to the substrate”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the method according to claim 14, wherein prior to forming, at the side of the substrate, the semiconductor pillars arranged in the array and extending in the direction perpendicular to the substrate, the method further comprises: forming, at the side of the substrate, a plurality of bitlines spaced from each other in a first direction and extending in a second direction, the first direction having a designed angle with respect to the second direction, and the first direction and the second direction both being parallel to the substrate; and forming, at the side of the substrate, the semiconductor pillars arranged in the array and extending in the direction perpendicular to the substrate comprises: forming, at a side of the bitlines distal to the substrate, a first dielectric layer, a metal layer, and a second dielectric layer stacked together, patterning the second dielectric layer, the metal layer, and the first dielectric layer to obtain a metal structure and first holes arranged in an array, such that side surfaces of the metal structure and upper surfaces of the bitlines are exposed in the first holes; and forming sacrificial dielectric layers on side walls of the first holes, and epitaxially forming the semiconductor pillars up the first holes at the side of the bitlines distal to the substrate,’ is material to the inventive concept of the application at hand to reduce induced leakage while preserving or improving on/off performance.
Claims 4, 9, 11, 16, 18, 21-22 and 24-25 are also objected to due to its dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0367479 A1 (Lee) - A semiconductor memory device is disclosed including a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.
US 2015/0263167 A1 (Miyata) - A semiconductor device is disclosed including a drain region, a source region, a channel region, a first gate insulator film provided on the channel region, a second gate insulator film provided on the channel region to be adjacent to the first gate insulator film on the source region side of the first gate insulator film, a first gate electrode provided on the first gate insulator film, and a second gate electrode provided on the second gate insulator film. An electrical thickness of the second gate insulator film is less than an electrical thickness of the first gate insulator film. A portion of the first gate electrode is provided on the second gate insulator film. A work function of the second gate electrode is higher than a work function of the first gate electrode.
US 20060163631 A1 (Chen) - A vertical pass transistor in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/06/2026
