Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, and 18-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Zhang et al. (CN112331714A, see attached machine translation).
Regarding Claim 1, Zhang teaches a display substrate (Fig. 2A, display substrate 10), comprising
a plurality of repetition units, wherein at least one repetition unit comprises a plurality of sub-pixels forming at least two pixel rows and two pixel columns (Fig. 2A, repetition units 100 formed of sub-pixels arrays having two pixel rows and two pixel columns),
at least one sub-pixel comprises a pixel drive circuit connected with a scan signal line, a first power supply line, a data signal line, and a compensation signal line (Fig. 3A teaches the sub-pixels P1-P4 are c connected with a scan signal line 150, a first power supply line 240 (left side), a data signal line DL, and a compensation signal line 230),
the scan signal line is configured to provide a scan signal to the pixel drive circuit (Paragraph 0159 (see attached machine translation) teaches the scan line 150 provides the first scan signal),
the first power supply line is configured to provide a power supply signal to the pixel drive circuit (Paragraph 0060 teaches the first power supply line 240 is configured to provide a power supply signal (voltage) to the pixel drive circuit),
the data signal line is configured to provide a data signal to the pixel drive circuit (Paragraph 0159 teaches the data signal line DL provides a data signal to the pixel drive),
and the compensation signal line is configured to provide a compensation signal to the pixel drive circuit (Paragraph 0161 teaches the compensation signal line 230 provides a compensation signal to the pixel drive circuit);
in a direction perpendicular to the display substrate the display substrate comprises at least a semiconductor layer and a plurality of conductive layers disposed on a base substrate, the first power supply line, the data signal line, and the compensation signal line are disposed on a side of the semiconductor layer close to the base substrate (Fig. 3B, Display substrate (all layers between 101 and 125) comprises a semiconductor layer 104, and a plurality of conductive layers (501-503) disposed on a base substrate 101. Paragraph 0294 teaches the second conductive layer 503, which is close to the base substrate, comprises the data signal line DL, the first power supply line 240 (left side), and the compensation signal line 230)
and the scan signal line is disposed on a side of the semiconductor layer away from the base substrate (Fig. 3B teaches the scan signal line 150 is disposed above the semiconductor layer 104, and therefore is on a side of 104 away from the base substrate 10).
Regarding Claim 4, Zhang teaches the display substrate according to claim 1, wherein the at least one repetition unit further comprises a power supply connection line, the power supply connection line is in a shape of a line extending along a pixel row direction, the first power supply line is in a shape of a line extending along a pixel column direction, and the power supply connection line is connected with the first power supply line to form a mesh structure for transmitting a first power supply signal in a mesh shape (Fig. 3A comprises a plurality of sub-pixels P1-P4, representing one repetition unit. First Power supply line 240 is connected to power supply connection line 241, which extends in a pixel row direction, forming a mesh structure with power supply line 240).
Regarding Claim 5, Zhang teaches the display substrate according to claim 4, wherein the power supply connection line and the first power supply line are disposed in different conductive layers, and the power supply connection line is connected with the first power supply line through a via (Zhang, paragraph n0213 teaches the power supply connection line 241 is located in the first conductive layer 501. Paragraph 0213 teaches the first power supply connection line is disposed in the second conductive layer 503. Paragraph 0215 teaches 240 and 241 are connected through a via hole number 3).
Regarding Claim 18, Zhang teaches a display apparatus, wherein the display apparatus comprises a display substrate according to claim 1 (Zhang, Fig. 2A, display substrate 10).
Regarding Claim 19, Zhang teaches a preparation method of a display substrate,
wherein the display substrate comprises a plurality of repetition units, at least one repetition unit comprises a plurality of sub-pixels forming at least two pixel rows and two pixel columns (Fig. 2A, repetition units 100 formed of sub-pixels arrays having two pixel rows and two pixel columns),
at least one sub-pixel comprises a pixel drive circuit connected with a scan signal line, a first power supply line, a data signal line, and a compensation signal line, respectively (Fig. 3A teaches the sub-pixels P1-P4 are c connected with a scan signal line 150, a first power supply line 240 (left side), a data signal line DL, and a compensation signal line 230),
wherein the scan signal line is configured to provide a scan signal to the pixel drive circuit (Paragraph 0159 teaches the scan line 150 provides the first scan signal),
the first power supply line is configured to provide a power supply signal to the pixel drive circuit (Paragraph 0060 teaches the first power supply line 240 is configured to provide a power supply signal (voltage) to the pixel drive circuit),
the data signal line is configured to provide a data signal to the pixel drive circuit (Paragraph 0159 teaches the data signal line DL provides a data signal to the pixel drive),
and the compensation signal line is configured to provide a compensation signal to the pixel drive circuit (Paragraph 0161 teaches the compensation signal line 230 provides a compensation signal to the pixel drive circuit);
the preparation method comprises: forming a semiconductor layer and a plurality of conductive layers on a base substrate (Fig. 3B, Display substrate (all layers between 101 and 125) comprises a semiconductor layer 104, and a plurality of conductive layers (501-503) disposed on a base substrate 101),
wherein the first power supply line, the data signal line, and the compensation signal line are disposed on a side of the semiconductor layer close to the base substrate (Fig. 3B, Display substrate (all layers between 101 and 125) comprises a semiconductor layer 104, and a plurality of conductive layers (501-503) disposed on a base substrate 101. Paragraph 0294 teaches the second conductive layer 503, which is close to the base substrate, comprises the data signal line DL, the first power supply line 240 (left side), and the compensation signal line 230),
and the scan signal line is disposed on a side of the semiconductor layer away from the base substrate (Fig. 3B teaches the scan signal line 150 is disposed above the semiconductor layer 104, and therefore is on a side of 104 away from the base substrate 10).
Regarding Claim 20, Zhang teaches the preparation method of the display substrate according to claim 19, wherein the forming the semiconductor layer and the plurality of conductive layers on the base substrate comprises:
forming a first conductive layer on the base substrate and a second conductive layer disposed on a side of the first conductive layer away from the base substrate (Fig. 3B and paragraph 0284-0293),
wherein the second conductive layer comprises at least the first power supply line, the data signal line, and the compensation signal line (Paragraph 0294 teaches the second conductive layer 503, which is close to the base substrate, comprises the data signal line DL, the first power supply line 240 (left side), and the compensation signal line 230);
forming a first insulation layer covering the second conductive layer and the semiconductor layer disposed on a side of the first insulation layer away from the base substrate (Fig. 3B, first insulation layer 204);
and forming a second insulation layer covering the semiconductor layer and a third conductive layer disposed on a side of the second insulation layer away from the base substrate (Fig. 3B, second insulation layer 203),
wherein the third conductive layer comprises at least the scan signal line (Fig. 3B teaches, third conductive layer 502 comprises the scan signal line 150).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claims 1, 4-5, and 18-20 above, and further in view of Liu et al. (CN 113972236 A, see attached machine translation).
Regarding Claim 2, Zhang teaches the display substrate according to claim 1, wherein in the direction perpendicular to the display substrate, the display substrate comprises
at least a first conductive layer, a second conductive layer, a first insulation layer, a semiconductor layer, a second insulation layer, and a third conductive layer disposed on the base substrate along a direction away from the base substrate, wherein the first power supply line, the data signal line, and the compensation signal line are disposed in the second conductive layer, and the scan signal line is disposed in the third conductive layer (Fig. 1A teaches in a direction perpendicular to the display substrate, a first conductive layer 501, a second conductive layer 503, a first insulation layer 201, a semiconductor layer 104, a second insulation layer 202 (or 203), and a third conductive layer 502 disposed in a direction away from base substrate 101. Paragraph 0294 teaches the first power supply line 240, the data signal line DL, and the compensation signal line 230 are disposed in the second conductive layer 503. Paragraph 0197 teaches the scan signal line 150 is disposed in the third conductive layer 502).
Zhang fails to teach the first conductive layer, second conductive layer, first insulation layer, semiconductor layer, second insulation layer, and third conductive layer are sequentially disposed on the base substrate along a direction away from the base substrate.
However, Liu teaches a display substrate wherein a first conductive layer, a second conductive layer, a first insulation layer, a semiconductor layer, a second insulation layer, and a third conductive layer disposed on the base substrate and sequentially disposed along a direction away from the base substrate (Liu, fig. 18 teaches a first conductive layer 51, second conductive layer 13/14, first insulation layer 41, semiconductor layer 12, second insulation layer 43, and third conductive layer 81 disposed on the base substrate 10 sequentially along a direction away from the base substrate).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Liu into the method of Zhang by forming the display substrate having a first conductive layer, a second conductive layer, a first insulation layer, a semiconductor layer, a second insulation layer, and a third conductive layer disposed on the base substrate and sequentially disposed along a direction away from the base substrate. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of reducing the number of patterning processes, shortening the process time, reducing the process cost, and facilitating mass production. (Liu, paragraph n0210, please see attached machine translation).
Claim(s) 6-7 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claims 1, 4-5, and 18-20 above, and further in view of Han et al. (Us Patent Pub 20190035874 A1).
Regarding Claim 6, Zhang teaches the display substrate according to claim 5, wherein the pixel drive circuit comprises at least a first transistor, a second transistor, a third transistor, and a storage capacitor, wherein a first electrode of the first transistor is connected with the data signal line, a second electrode of the first transistor is connected with a gate electrode of the second transistor and a first end of the storage capacitor respectively, a first electrode of the second transistor is connected with the first power supply line, a second electrode of the second transistor is connected with a second electrode of the third transistor and a second end of the storage capacitor respectively, and a first electrode of the third transistor is connected with the compensation signal line (Fig. 2C and 3B teaches a first transistor T2, a second transistor T1, a third transistor T3, and a storage capacitor Cst. Paragraph 0162 teaches a first electrode of the first transistor T2 is connected with data signal line to receive a data signal GT, and a second electrode of the first transistor T2 is connected with a gate electrode of the second transistor T1 and a first end of the storage capacitor. A first electrode of the second transistor T1 is connected to the first power supply line VDD to receive a first power supply voltage V1, a second electrode of the second transistor T1 is connected with a second electrode of the third transistor T3 and a second end of the storage capacitor. And a first electrode of the third transistor T3 is connected with the compensation signal line 230).
Zhang fails to teach the display substrate wherein in a pixel drive circuit of at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected with a same scan signal line.
However, Han teaches a display substrate wherein in a pixel drive circuit of at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected with a same scan signal line (Han, Fig. 1 and paragraph 0034 teach the gate electrode of the first transistor TFT ST and the gate electrode of the third transistor TFT ET can be connected to each other so as to be shared on the scan line).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Han into the method of Zhang by forming the display substrate wherein in a pixel drive circuit of at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected with a same scan signal line. The ordinary artisan would have been motivated to modify Zhang in the manner set forth above for at least the purpose of arranging the driving circuit components such that the light emitting diode display can selectively disconnect one section of a scan line to darken a defective pixel when a defect occurs in a pixel provided with thin film transistors (TFTs). (Han, paragraph 0002).
Regarding Claim 7, Zhang in view of Han teaches the display substrate according to claim 6, wherein in a plurality of pixel drive circuits of at least one pixel row, gate electrodes of a plurality of first transistors and gate electrodes of a plurality of third transistors are connected with a same scan signal line, or in a plurality of pixel drive circuits of at least one repetition unit, gate electrodes of a plurality of first transistors and gate electrodes of a plurality of third transistors are connected with a same scan signal line (Han, Fig. 2 teaches a subpixel row comprising a plurality of sub pixels connected by scan line SL. Paragraph 0040 teaches the plurality of subpixels (R, W, G, and B) aligned in a row constitute a pixel, and that these unit pixels are repeatedly aligned. Therefore, the scan line SL would continue with the configuration of Fig. 1 across all of the subpixels of the aligned pixel row, wherein SL is arranged such that the gate electrode of the first transistor TFT ST and the gate electrode of the third transistor TFT ET of each of the sub pixels in the pixel row can be connected to each other).
Regarding Claim 9, Zhang in view of Han teaches the display substrate according to claim 6, wherein the scan signal line, the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor are disposed in a same layer (Zhang, paragraph 0183 teaches the second conductive layer includes the gate electrode of the first transistor T2, the second transistor T1, and the third transistor T3. Paragraph 0197 teaches the second conductive layer also includes scan signal line 150).
Regarding Claim 10, Zhang in view of Han teaches the display substrate according to claim 6, wherein in at least one repetition unit, gate electrodes of a plurality of first transistors and gate electrodes of a plurality of third transistors of adjacent pixel rows are connected with a same scan signal line (Han, paragraph 0058 and Fig. 3 teach a repetition unit (any of the sub pixels arranged in a 2 x 2 grid) comprising pixel drive circuits of adjacent pixel rows wherein the gate electrodes of a plurality of first transistors TFT ST and gate electrodes of a plurality of third transistors TFT ET are connected with a same scan signal line SL).
Regarding Claim 11, Zhang in view of Han teaches the display substrate according to claim 10, wherein the plurality of repetition units comprise an (n-1)-th repetition unit row, an n-th repetition unit row, and an (n+1)-th repetition unit row, wherein n is a positive integer greater than 1, the n-th repetition unit row comprises a first pixel row and a second pixel row, the first pixel row is located on a side of the second pixel row close to the (n-1)-th repetition unit row, the second pixel row is located on a side of the first pixel row close to the (n+1)-th repetition unit row (Zhang, Fig. 2A teaches a plurality of repetition units 100. These repetition units are comprised of sub-pixels arranged in 2 x 2 matrix. Fig. 3A and paragraph 0173 teaches these sub-pixels are distributed along the D1 and D2 direction, forming a pixel array. This pixel array is arranged such that the plurality of repetition units comprise an (n-1)-th repetition unit row, an n-th repetition unit row, and an (n+1)-th repetition unit row, wherein n is a positive integer greater than 1, the n-th repetition unit row comprises a first pixel row and a second pixel row, the first pixel row is located on a side of the second pixel row close to the (n-1)-th repetition unit row, the second pixel row is located on a side of the first pixel row close to the (n+1)-th repetition unit row);
a first gate electrode and a third gate electrode comprised in the first pixel row in the n-th repetition unit row are all located on a side of the scan signal line close to the (n-1)-th repetition unit row, and a first gate electrode and a third gate electrode comprised in the second pixel row in the n-th repetition unit row are all located on a side of the scan signal line close to the (n+1)-th repetition unit row (The combination of Zhang in view of Han would teach this pixel array arrangement would comprise a first gate electrode (of the first transistor TFT ST) and a third gate electrode (of the third transistor TFT ET) comprised in the first pixel row in the n-th repetition unit row are all located on a side of the scan signal line SL close to the (n-1)-th repetition unit row, and a first gate electrode and a third gate electrode comprised in the second pixel row in the n-th repetition unit row are all located on a side of the scan signal line close to the (n+1)-th repetition unit row).
Regarding Claim 12, Zhang in view of Han teaches the display substrate according to claim 6, wherein the first end of the storage capacitor comprises a first electrode plate and a third electrode plate, and the second end of the storage capacitor comprises a second electrode plate, an orthographic projection of the second electrode plate on the base substrate is at least partially overlapped with an orthographic projection of the first electrode plate on a plane of the display substrate, the first electrode plate and the second electrode plate form a first capacitor, an orthographic projection of the second electrode plate on the plane of the display substrate is at least partially overlapped with an orthographic projection of the third electrode plate on the plane of the display substrate, the third electrode plate and the second electrode plate form a second capacitor, the first electrode plate is respectively connected with the third electrode plate, the second electrode of the first transistor, and the gate electrode of the second transistor, the second electrode plate is respectively connected with the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor construct a storage capacitor with a parallel structure (Zhang, Fig. 2C teaches storage capacitor Cst, wherein the first end of the storage capacitor comprises a first electrode plate Cc and a third electrode plate Cb, and the second end of the storage capacitor comprises a second electrode plate Ca. Fig. 3B teaches an orthographic projection of the second electrode plate Ca on base substrate 101 is overlapped with an orthographic projection of the first electrode plate Cc. Fig. 3B also teaches the first electrode plate Cc and the second electrode plate Ca form first capacitor C1, and an orthographic projection of the second electrode plate Ca on the plane of the display substrate is at least partially overlapped with an orthographic projection of the third electrode plate Cb on the plane of the display substrate. Further, Fig 3B. also teaches the third electrode plate Cb and the second electrode plate Ca form a second capacitor C2. Fig. 3B and paragraph 0187 teaches Cc is connected with Cb, and through Cb and 720 is also electrically connected with the second electrode T2s of the first transistor T2, and the gate electrode T1g of the second transistor T1. Fig. 3B. further teaches the second electrode plate Ca is respectively connected to the second electrode T1d of the second transistor T1 and the second electrode T3d of the third transistor T3 (paragraph 0212 teaches T3 and Cb are connected as a whole, therefore since Ca and Cb are connected, Ca is electrically connected to T3d of T3). Paragraph n0182 teaches Cst has a parallel structure).
Claim(s) 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Han as applied to claims 6-7 and 9-12 above, and further in view of Cho et al. (US Patent Pub 20200184903 A1) and Liu.
Regarding Claim 13, Zhang in view of Ha teaches the display substrate according to claim 12, wherein in the direction perpendicular to the display substrate, the display substrate comprises a drive circuit layer disposed on the base substrate, a color film structure layer disposed on a side of the drive circuit layer away from the base substrate, and a light emitting structure layer disposed on a side of the color film structure layer away from the base substrate, the light emitting structure layer comprises at least a fourth conductive layer and a pixel definition layer sequentially disposed along the direction away from the base substrate; in at least one sub-pixel, the first electrode plate is disposed in the first conductive layer, the second electrode plate is disposed in the semiconductor layer, and the third electrode plate is disposed in the fourth conductive layer (Zhang, Fig. 3B and paragraph 0045 teaches a color film structure 190 disposed on the drive circuit layer (the drive circuit layer is comprised of first conductive layer 501, semiconductor layer 104, second conductive layer 503, and third conductive layer 502) away from base substrate 101 and having the light emitting structure disposed on a side of 190 away from the base substrate. The light emitting structure 125 comprises a fourth conductive layer (portion of 503 connected to 123) and a pixel definition layer 206. Fig. 3B teaches the first electrode plate is disposed in the first conductive layer 501, the second electrode plate Ca is disposed in the semiconductor layer 104, the third electrode plate Cb is disposed in the fourth conductive layer (portion of 503 connected to 123)).
Zhang in view of Han fails to teach the third plate is electrically connected to the first plate through a via.
However, Cho teaches a display device having the third plate is electrically connected to the first plate through a via (Cho, Fig. 6 teaches third plate P3 is connected to first plate P1 through a via (Fig. 7, H2)).
It would have been obvious to one of ordinary skill in the art at the time of invention to combine the teachings of Cho into the method of Zhang in view of Han by forming the display device wherein having the third plate is electrically connected to the first plate through a via. The ordinary artisan would have been motivated to modify Zhang in view of Han in the manner set forth above for at least the purpose of generating dual storage capacitors (Cho, paragraph 0177).
Zhang in view of Han and Cho fail to teach the drive circuit layer comprises at least a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially disposed along a direction away from the base substrate.
However, Liu teaches a display substrate with a drive circuit layer comprising a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially disposed along a direction away from the base substrate (Liu, Fig. 18 teaches a first conductive layer 51, second conductive layer 13/14, semiconductor layer 12, and third conductive layer sequentially disposed along a direction away from the base substrate).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Liu into the method of Zhang in view of Han and Cho by forming the display substrate with a drive circuit layer comprising a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer sequentially disposed along a direction away from the base substrate. The ordinary artisan would have been motivated to modify Zhang in view of Han and Cho in the manner set forth above for at least the purpose of reducing the number of patterning processes, shortening the process time, reducing the process cost, and facilitating mass production. (Liu, paragraph n0210, please see attached machine translation).
Regarding Claim 14, Zhang in view of Han, Cho, and Liu teaches the display substrate according to claim 13, wherein a plurality of sub-pixels in at least one repetition unit comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel and the second sub-pixel form a first pixel row, the third sub-pixel and the fourth sub-pixel form a second pixel row, the first sub-pixel and the third sub-pixel form a first pixel column, and the second sub-pixel and the fourth sub-pixel form a second pixel column (Han, Fig. 3 teaches first sub-pixel P1, second sub-pixel P3, third sub-pixel P4, and fourth sub-pixel P2. the first sub-pixel and the second sub-pixel form a first pixel row, the third sub-pixel and the fourth sub-pixel form a second pixel row, the first sub-pixel and the third sub-pixel form a first pixel column, and the second sub-pixel and the fourth sub-pixel form a second pixel column);
the color film structure layer comprises at least a red color film layer, a blue color film layer, and a green color film layer, wherein the red color film layer comprises at least a red filter disposed in the first sub-pixel, the blue color film layer comprises at least a blue filter disposed in the second sub-pixel, and the green color film layer comprises at least a green filter disposed in the fourth sub-pixel (Zhang, paragraph 0307 teaches the color film layers 190 corresponding to red, green and blue color filters. The combination of Zhang and Han teaches a red, blue, and a green color film layer over the respective sub-pixels (Han, fig. 3, R, B, and G respectively). The red color filter is disposed in first sub-pixel P1, the blue color film layer is disposed in the second sub -pixel P3, and the green color film layer is disposed in the fourth sub-pixel P2.).
Regarding Claim 15, Zhang in view of Han, Cho, and Liu teaches the display substrate according to claim 14, wherein the red color film layer further comprises a shielding strip, a first shielding block, a second shielding block, a third shielding block, and a fourth shielding block (Zhang, see annotated image of Fig. 3A below);
an orthographic projection of the shielding strip on the base substrate is at least partially overlapped with an orthographic projection of the scan signal line on the base substrate, an orthographic projection of the first shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the first sub-pixel on the base substrate, an orthographic projection of the second shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the second sub-pixel on the base substrate, an orthographic projection of the third shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the third sub-pixel on the base substrate, and an orthographic projection of the fourth shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the fourth sub-pixel on the base substrate (Zhang, See annotated figure 3A below).
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Regarding Claim 16, Zhang in view of Han, Cho, and Liu teaches the display substrate according to claim 14, wherein the red color film layer further comprises a shielding strip, a first shielding block, and a third shielding block, and the blue color film layer further comprises a second shielding block and a fourth shielding block (Zhang, Fig. 3A, see annotated figure above);
an orthographic projection of the shielding strip on the base substrate is at least partially overlapped with an orthographic projection of the scan signal line on the base substrate, an orthographic projection of the first shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the first sub-pixel on the base substrate, an orthographic projection of the second shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the second sub-pixel on the base substrate, an orthographic projection of the third shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the third sub-pixel on the base substrate, and an orthographic projection of the fourth shielding block on the base substrate is at least partially overlapped with an orthographic projection of a second transistor in the fourth sub-pixel on the base substrate (Zhang, Fig. 3A, see annotated figure above).
Regarding Claim 17, Zhang in view of Han, Cho, and Liu teaches the display substrate according to claim 13, wherein in at least one sub-pixel, the fourth conductive layer comprises at least the third electrode plate, and a pixel opening exposing the third electrode plate is disposed on the pixel definition layer (Zhang, Fig. 3B teaches a cross section of a pixel drive circuit of at least one sub-pixel wherein the fourth conductive layer (portion of 503 connected to 123) comprises at least the third electrode plate Cb, and a pixel opening (not shown but described in paragraph 0240) which exposes the third electrode plate disposed on the pixel definition layer 206);
in at least one repetition unit, at least one pixel slot is disposed on the pixel definition layer, the pixel slot comprises any one or more of: a first pixel slot extending along a pixel row direction, and a second pixel slot extending along a pixel column direction (Zhang, Fig. 3a. first pixel slot 12 disposed on the pixel definition layer 206. Paragraph 211 of applicant’s own specification teaches the pixel slot is formed to eliminate lateral leakage and lateral crosstalk of sub-pixels. Paragraph 0226 teaches 12 is used to avoid color mixing of light and light leakage. Therefore, 12 is a pixel slot).
Allowable Subject Matter
Claims 3 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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