CTNF 18/705,574 CTNF 101438 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1-3, 5, 8 and 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park(US20200052056A1) and Zhao(US20230329037A1) . Regarding Claim 1, Park teaches in FIG 1, FIG 3 and FIG 4, a display substrate, comprising: a base substrate (FIG 4; 110; ¶[0071]); and a plurality of sub-pixels (FIG 1; 30; ¶[0039]) arranged in an array on the base substrate (FIG 4; 110; ¶[0071]); wherein each of the sub-pixels (FIG 1; 30; ¶[0039]) comprises a light-emitting device (FIG 1; 100; ¶[0039]) and a pixel driving circuit (FIG 3; sub-pixel circuit; ¶[0040]) for driving the light-emitting device, the pixel driving circuit (FIG 3; sub-pixel circuit; ¶[0040]) comprises at least two oxide transistors (FIG 3; Tr1, Tr2, Tr3; ¶[0044]) and a storage capacitor (FIG 3; CST; ¶[0044]); at least two oxide transistors (FIG 4; 650; ¶[0071]; first oxide transistor) (FIG 4; 250; ¶[0071]; second oxide transistor) (FIG 4; 255; ¶[0071]; third oxide transistor) Park does not teach wherein the storage capacitor includes a first electrode and a second electrode sequentially facing away from the base substrate and arranged opposite to each other; in the at least two oxide transistors, a distance between a gate of one oxide transistor and an active layer of the one oxide transistor is different from a distance between a gate of at least one of other oxide transistors and an active layer of the at least one of other oxide transistors; and the one oxide transistor in the at least two oxide transistors with a greater distance between the gate and the active layer is arranged above the second electrode. Zhao teaches FIG 4, wherein the storage capacitor (FIG 4; 2; ¶[0055]) includes a first electrode (FIG 4; 16; ¶[0055]) and a second electrode (FIG 4; 18; ¶[0055]) sequentially facing away from the base substrate and arranged opposite to each other (FIG 4; 16 and 18; ¶[0055]); in the at least two transistors, a distance between a gate (FIG 4; 15; ¶[0056]) of one transistor (FIG 4; T(1); ¶[0087]) and an active layer (FIG 4; 13; ¶[0072]) of the one transistor (FIG 4; T(1); ¶[0087]) is different from a distance between a gate (FIG 4; 22; ¶[0110]) of at least one of other transistors (FIG 4; T(3); ¶[0087]) and an active layer (FIG 4; 20; ¶[0110]) of the at least one of other transistors (FIG 4; T(3); ¶[0087]); and the one transistor (FIG 4; T(3); ¶[0087]) in the at least two oxide transistors with a greater distance between the gate and the active layer is arranged above the second electrode (FIG 4; 18; ¶[0055]). It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors and the prior art of Zhao, a semiconductor device with a storage capacitor including a first electrode and a second electrode and two transistors with different distances between the gate and the active layer. This combination produces a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors with different distances between the gate and the active layer and storage capacitor including a first electrode and a second electrode. The sub-pixel structure containing the storage capacitor and multiple transistors to support the display Zhao¶[0054]). Regarding Claim 2 , Park and Zhao teach the display substrate according to claim 1 . Park does not teach wherein the second electrode partially overlaps with active layers of the at least two oxide transistors. Zhao teaches in FIG 4 wherein the second electrode (FIG 4; 18; ¶[0055]) partially overlaps with active layers of the at least two oxide transistors (FIG 4; T(1); ¶[0087]) (FIG 4; T(3); ¶[0087]). It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors and the prior art of Zhao, a semiconductor device with a storage capacitor including a first electrode and a second electrode partially overlapping with active layers of at least two oxide transistors. This combination produces a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors with different distances between the gate and the active layer and storage capacitor including a first electrode and a second electrode partially overlapping with active layers of at least two oxide transistors. The sub-pixel structure containing the storage capacitor and multiple transistors to support the display Zhao¶[0054]). The second electrode partially overlapping with active layers of at least two oxide transistors influences the electron flow in the transistors effecting the performance of the device. Regarding Claim 3 , Park and Zhao teach the display substrate according to claim 2 . Park teaches in FIG 4, at least two oxide transistors (FIG 4; 650; ¶[0047]) (FIG 4; Tr1; 250; ¶[0052]) (FIG 4; 255; Tr6; ¶[0064]) Park does not teach wherein the pixel driving circuit further comprises at least one polysilicon transistor coupled with the at least two oxide transistors; a gate of the at least one polysilicon transistor is arranged in a same layer as the first electrode, and the at least two oxide transistors are arranged on a side of the second electrode facing away from the base substrate. Zhao teaches in FIG 4, wherein the pixel driving circuit further comprises at least one polysilicon transistor (FIG 4; 1; ¶[0055]) coupled with the at least two oxide transistors (¶[0009]; at least 1 transistor includes at least two oxide transistors); a gate (FIG 4; 15; ¶[0056]) of the at least one polysilicon transistor is arranged in a same layer as the first electrode (FIG 4; 16; ¶[0056]), and the at least one oxide transistor (FIG 4; 3; ¶[0055]) is arranged on a side of the second electrode (FIG 4; 18; ¶[0055]) facing away from the base substrate (FIG 4; 10; ¶[0055]). It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors and the prior art of Zhao, a semiconductor device with a pixel driver circuit comprising a polysilicon transistor and two oxides transistors arranged on a side of the second electrode facing away from the base substrate. This combination produces a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors with a pixel driver circuit comprising a polysilicon transistor and two oxides transistors arranged on a side of the second electrode facing away from the base substrate. The sub-pixel structure containing the storage capacitor and multiple transistors to support the display Zhao¶[0054]). Having multiple transistors made of a variety of materials on a single semiconductor device allows for the device to perform complex function for a variety of applications. Regarding Claim 5, Park and Zhao teach the display substrate according to Claim 1 . Park does not teach wherein an orthographic projection of the second electrode on the base substrate completely falls within an orthographic projection of the first electrode on the base substrate. Zhao teaches in FIG 4 wherein an orthographic projection of the second electrode (FIG 6; 18; F1 ¶[0055]) on the base substrate completely falls within an orthographic projection of the first electrode (FIG 6; 16; F1; ¶[0055]) on the base substrate. It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors and the prior art of Zhao, a semiconductor device orthographic projection of the second electrode on the base substrate completely falls within an orthographic projection of the first electrode on the base substrate. This combination produces a semiconductor device containing a plurality of sub-orthographic projection of the second electrode on the base substrate completely falls within an orthographic projection of the first electrode on the base substrate. Having the orthographic projection of an active layer within the orthographic projection of an electrode improves the performance of the semiconductor device Zhao¶[0065]. Regarding Claim 8 , Park and Zhao teach a display device, comprising: the display substrate according to claim 1 . It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors and the prior art of Zhao, a semiconductor device with a storage capacitor including a first electrode and a second electrode and two transistors with different distances between the gate and the active layer. This combination produces a semiconductor device containing a plurality of sub-pixels with at least two oxide transistors with different distances between the gate and the active layer and storage capacitor including a first electrode and a second electrode. The sub-pixel structure containing the storage capacitor and multiple transistors to support the display Zhao¶[0054]). Regarding Claim 9 , Park and Zhao teach a method for manufacturing the display substrate according to claim 1 , comprising: Park teaches in FIG 4, at least two oxide transistors (FIG 4; 650; ¶[0071]; first oxide transistor) (FIG 4; 250; ¶[0071]; second oxide transistor) (FIG 4; 255; ¶[0071]; third oxide transistor) Park does not teach forming patterns of the first electrode and the second electrode of the storage capacitor and patterns of active layers of the at least two oxide transistors on the base substrate, sequentially; and forming a pattern of a gate insulating layer on a side of the active layers of the at least two oxide transistors facing away from the base substrate, so that in the at least two oxide transistors, a distance between a gate and an active layer of one transistor arranged above the second electrode is greater than a distance between a gate and an active layer of other transistors. Zhao teaches in FIG 4, forming patterns of the first electrode (FIG 4; 16; ¶[0055]) and the second electrode (FIG 4; 18; ¶[0055]) of the storage capacitor (FIG 4; 10; ¶[0065]) and patterns of active layers (FIG 4; 13 and 20; ¶[0072] ¶[0065]) of the transistor on the base substrate (FIG 4; 10; ¶[0065]), sequentially; and forming a pattern of a gate insulating layer (FIG 4; 17 and 21; ¶[0088]) on a side of the active layers (FIG 4; 13 and 20; ¶[0072] ¶[0065]) of the transistor facing away from the base substrate (FIG 4; 10; ¶[0065]), so that in the transistor, a distance between a gate (FIG 4; 22; ¶[0110]) and an active layer (FIG 4; 20; ¶[0110]) of one transistor (FIG 4; T(3); ¶[0087]) arranged above the second electrode is greater than a distance between a gate (FIG 4; 15; ¶[0056]) and an active layer (FIG 4; 13; ¶[0072]) of other transistors (FIG 4; T(1); ¶[0087]). It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Park, a semiconductor device containing a plurality of sub-and the prior art of Zhao, a method to manufacture the display substrate by forming the first and second electrodes, storage capacitor, active layers and gate insulating layers. This combination produces a semiconductor device containing a plurality of sub-pixels with and a method to manufacture the display substrate by forming the first and second electrodes, storage capacitor, active layers and gate insulating layers. The manufacturing method saves on space layout, ensures low power consumption and is simple Zhao¶[0095] . Allowable Subject Matter 07-43 Claim 4, 6, 7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 4, the prior art of record Choi(US20110079787A1), either singularly or in combination, does not disclose or suggest the combination of limitations wherein orthographic projections of the active layers of the at least two oxide transistors on the base substrate completely fall within an orthographic projection of an active layer of the at least one polysilicon transistor on the base substrate. Choi discloses active layers of the at least two oxide transistors on the base substrate completely fall within an orthographic projection. Regarding claim 6, the prior art of record Hiramatsu(US20190206975A1), either singularly or in combination, does not disclose or suggest the combination of limitations the display substrate according to claim 5 , wherein the at least two oxide transistors comprise a compensation transistor and a first reset transistor, and the pixel driving circuit further comprises a driving transistor, a first light emitting control transistor, a second light emitting control transistor, a data writing transistor, and a second reset transistor, which are polysilicon transistors; wherein: the compensation transistor is respectively coupled between a gate of the driving transistor and a first electrode of the driving transistor, and a gate of the compensation transistor is coupled with a first scanning control terminal; the first reset transistor is respectively coupled between the gate of the driving transistor and an initialization signal terminal, and a gate of the first reset transistor is coupled with the first scanning control terminal; the storage capacitor is respectively coupled between a first power supply terminal and the gate of the driving transistor; the first light emitting control transistor is respectively coupled between the first power supply terminal and a second electrode of the driving transistor, and a gate of the first light emitting control transistor is coupled with a light emitting control terminal; the second light emitting control transistor is respectively coupled between a first electrode of the driving transistor and a first electrode of the light-emitting device, and a gate of the second light emitting control transistor is coupled with the light emitting control terminal; the data writing transistor is respectively coupled between the second electrode of the driving transistor and a data signal terminal, and a gate of the data writing transistor is coupled with a second scanning control terminal; the second reset transistor is respectively coupled between the first electrode of the light- emitting device and the initialization signal terminal, and a gate of the second reset transistor is coupled with the second scanning control terminal; and a second electrode of the light-emitting device is coupled with a second power supply terminal. Hiramatsu teaches the first light emitting control transistor is respectively coupled between the first power supply terminal Regarding Claim 7 , the prior art of Hiramatsu(US20190206975A1) either singularly or in combination, does not disclose or suggest the combination of limitations The display substrate according to claim 6, wherein the compensation transistor and the first reset transistor are both N-type transistors; and the driving transistor, the first light emitting control transistor, the second light emitting control transistor, the data writing transistor and the second reset transistor are all P-type transistors. Hiramatsu discloses driving transistor, the first light emitting control transistor. Regarding Claim 10 , the prior art of record Zhao(US20230329037A1), either singularly or in combination, does not disclose or suggest the combination of limitations The manufacturing method according to claim 9 , wherein forming the pattern of the gate insulating layer on the side of the active layers of the at least two oxide transistors facing away from the base substrate, comprises: depositing the gate insulating layer with a first thickness on the side of the active layers of the at least two oxide transistors facing away from the base substrate; coating a photoresist on the gate insulating layer; patterning the photoresist by using a composition process, and removing the photoresist at positions corresponding to the other transistors, to form a pattern of the photoresist; etching the gate insulating layer at the positions corresponding to the other transistor by a third thickness according to the pattern of the photoresist, wherein a difference between the first thickness and the third thickness is a second thickness, and the first thickness is greater than the second thickness; and removing the pattern of the photoresist to form the pattern of the gate insulating layer. Zhao discloses depositing the gate insulating layer with a first thickness on the side of the active layers of the at least two oxide transistors facing away from the base substrate wherein a difference between the first thickness and the third thickness is a second thickness, and the first thickness is greater than the second thickness Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure : Yamazaki(US20210351224A1) : This reference teaches a semiconductor device comprising two transistors and a photoelectric conversion device. Hanyu(US20180219029A1): This reference teaches a semiconductor device with two transistors. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at 5712727925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.Q.R./Examiner, Art Unit 2817 /RATISHA MEHTA/Primary Examiner, Art Unit 2817 Application/Control Number: 18/705,574 Page 2 Art Unit: 2817 Application/Control Number: 18/705,574 Page 3 Art Unit: 2817 Application/Control Number: 18/705,574 Page 4 Art Unit: 2817 Application/Control Number: 18/705,574 Page 5 Art Unit: 2817 Application/Control Number: 18/705,574 Page 6 Art Unit: 2817 Application/Control Number: 18/705,574 Page 7 Art Unit: 2817 Application/Control Number: 18/705,574 Page 8 Art Unit: 2817 Application/Control Number: 18/705,574 Page 9 Art Unit: 2817 Application/Control Number: 18/705,574 Page 10 Art Unit: 2817
Prosecution Insights