DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 10/28/2024 and 5/19/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Preliminary Amendment & Claims’ Status
Applicant’s 4/29/2024 preliminary amendment to amend the Specification, Claims, and Abstract is acknowledged.
Claims 1-20 are currently pending and being examined. Claims 11 and 13-14 have been amended. Claims 15-20 have been newly added. No claims have been cancelled.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract of the disclosure is objected to because of the use of legal phraseology, such as “said” (see line 7 of the instant abstract). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-11, and 13-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LV et al (US 2025/0351687 A1, hereafter LV).
Re Claim 1, LV discloses a display substrate (FIG. 8, with reference to FIG. 4; [0090]), comprising:
a base substrate (101; [0058]);
a shielding layer (Z1; [0059]), wherein the shielding layer (Z1) is provided on a side of the base substrate (101; [0059]) and comprises a plurality of shielding parts (Z11; [0076]) provided at intervals ([0076]), a plurality of first connecting lines (Z12.1, Z12.2, see FIG. Z1 below; [0076]), and an edge line (Z13; [0076]); the plurality of shielding parts (Z11) are connected by the first connecting lines (Z12.1, Z12.2; [0076]); and the edge line (Z13) is provided on peripheries of the plurality of shielding parts (Z11) and connected to end parts of the first connecting lines (Z12.1, Z12.2; [0076]); and
a driving thin film transistor (T1; [0064]), wherein the driving thin film transistor (T1) comprises an active layer (201; [0063]) provided on a side of the shielding layer (Z1) away from the base substrate (101; [0064]); and an orthographic projection of each shielding part (Z11) on the base substrate (101) covers at least a partial area of an orthographic projection of the active layer (201) on the base substrate (101; [0066]).
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FIG. Z1: Annotated version of FIG. 4 of LV
Re Claim 2, LV discloses the display substrate according to Claim 1, while further disclosing wherein a plurality of driving thin film transistors (T1) are provided ([0064]), and each of the plurality of driving thin film transistors (T1) comprises an active layer (201; [0063]); and
the orthographic projection of each shielding part (Z11) on the base substrate (101) respectively covers at least a partial area of the orthographic projection of the active layer (201) on the base substrate (101; [0066]).
Re Claim 3, LV discloses the display substrate according to Claim 1, while further disclosing wherein a width of the edge line (Z13; [0084]) is 3 to 5 times a width of the first connecting lines (Z12.1, Z12.2; [0061], thickness of Z1 being the width of the first connecting lines, for example 3000 angstroms would qualify).
Re Claim 5, LV discloses the display substrate according to Claim 1, while further disclosing wherein the plurality of shielding parts (Z11) are arranged in an array ([0076]) in a first direction (left to right across page of FIG. 4; [0076]) and a second direction (up and down across page of FIG. 4; [0076]), and the first connecting lines (Z12.1, Z12.2) further comprise:
a plurality of first connecting segments (Z12.1) extending in the first direction (left to right across page of FIG. 4; [0076]) and extending to the edge line (Z13; [0076]) and connecting the shielding parts (Z11) arranged in the first direction (left to right across page of FIG. 4; [0076]); and
a plurality of second connecting segments (Z12.2) extending in the second direction (up and down across page of FIG. 4; [0076]) and extending to the edge line (Z13; [0076]) and connecting the shielding parts (Z11) arranged in the second direction (up and down across page of FIG. 4; [0076]);
wherein the first direction (left to right across page of FIG. 4) intersects with the second direction (up and down across page of FIG. 4; [0076]).
Re Claim 6, LV discloses the display substrate according to Claim 5, while further disclosing wherein the shielding layer (Z1) further comprises a second connecting line (Z12.3, Z12.4, see FIG. Z1; [0076]), an end part of the second connecting line (Z12.3, Z12.4) is not connected to the edge line (Z13; [0076]), and the second connecting line (Z12.3, Z12.4) comprises a third connecting segment (Z12.3) extending in the first direction (left to right across page of FIG. 4; [0076]) and a fourth connecting segment (Z12.4) extending in the second direction (up and down across page of FIG. 4; [0076]); and
wherein the third connecting segment (Z12.3) is located between a first connecting segment (Z12.1) and the edge line (Z13; [0076]), and connects the shielding parts (Z11) arranged in the first direction (left to right across page of FIG. 4; [0076]); and the fourth connecting segment (Z12.4) is located between a second connecting segment (Z12.2) and the edge line (Z13; [0076]), and connects the shielding parts (Z11) arranged in the second direction (up and down across page of FIG. 4; [0076]).
Re Claim 7, LV discloses the display substrate according to Claim 6, while further disclosing wherein the third connecting segment (Z12.3) and the fourth connecting segment (Z12.4) are straight lines ([0059]) or are curved in partial areas ([0090]).
Re Claim 9, LV discloses the display substrate according to Claim 1, while further disclosing wherein the edge line (Z13) is a smooth curve ([0076]).
Re Claim 10, LV discloses the display substrate according to Claim 1, while further disclosing wherein an included angle between the edge line (Z13) and the first connecting lines (Z12.1, Z12.2) at an intersection is less than or equal to 90 degrees ([0076], by nature of Z13 being curved around Z12).
Re Claim 11, LV discloses the display substrate according to Claim 1, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 13, LV discloses a display panel (FIG. 8; [0047]), comprising the display substrate according to Claim 1.
Re Claim 14, LV discloses a display apparatus (FIG. 8; [0047]), comprising the display substrate according to Claim 1.
Re Claim 15, LV discloses the display substrate according to Claim 2, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 16, LV discloses the display substrate according to Claim 3, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 17, LV discloses the display substrate according to Claim 4, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 18, LV discloses the display substrate according to Claim 5, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 19, LV discloses the display substrate according to Claim 6, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Re Claim 20, LV discloses the display substrate according to Claim 7, while further disclosing wherein the driving thin film transistor (T1) further comprises a source (208; [0063]) and a drain (208; [0063]), both of the source (208) and the drain (208) are electrically connected to the active layer (201) by through holes ([0063]); and an orthographic projection of the through holes on the base substrate (101) and an orthographic projection of the edge line (Z13) on the base substrate (101) have no overlapping region ([0063], specifically the orthographic projection of stated elements as shown in FIG. 8).
Allowable Subject Matter
Claims 4, 8, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 4, the prior art cannot anticipate, or render obvious, the limitations of: wherein the width of the edge line is 18 to 22 microns, in combination with the additionally claimed features of Claim 4.
Re Claim 8, the prior art cannot anticipate, or render obvious, the limitations of: provided at a position where part of the first connecting line intersects with the edge line, in combination with the additionally claimed features of Claim 8.
Re Claim 12, the prior art cannot anticipate, or render obvious, the limitations of: wherein a minimum distance between the edge line and the through holes is greater than or equal to 2.5 microns, in combination with the additionally claimed features of Claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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