DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Display Substrate Having Mesh Structured Initial Signal Lines and Initial Connection Lines and Display Apparatus Comprising the Same
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5-9 and 11-13 rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “two first initial connection lines passes through, along a centerline of the second direction, a signal body line of a second initial connection line located between the two first initial connection lines”, which appears inconsistent with the specification and figures (Fig 6 and the fourth full paragraph of page 22). The Examiner understands that it is a centerline of two first initial connection lines that passes through a signal body line, and not two first initial connections lines that pass through a signal body line. Because the claim is not in agreement with the specification, and the Examiner is uncertain of an embodiment in accordance with the claim language, the scope of the claim is unclear.
For the purposes of examination, the limitation will be interpreted, in accordance with the fourth full paragraph of page 22 of the specification, as “a centerline extending along the second direction between two first initial connection lines passes through a signal body line of a second initial connection line located between the two first initial connection lines”.
Regarding claims 6-9 and 11-13, note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim 6 is additionally rejected because the overlapping is unclear. That is, claim 6 recites “the orthographic projection of the first initial signal line on the substrate is overlapped, at least partially, with an orthographic projection of the second plate of the capacitor on the substrate”. Support for this limitation is found in the second to last paragraph of page 22 of the specification, which says “as shown in FIGs 6 to 9”, the first initial signal line INIT1 is overlapped with second plate C2; however, such overlapping is not recognized by the Examiner in these or other figures. Fig 7, specifically, depicts INIT1 and C2 on a same layer and separated from one another. Because the support says the limitation is included in these figures, but it is not apparent, the scope of the limitation is indefinite, and examination for prior art has not been completed.
Regarding claims 7-9 and 11-13, note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Prior art examination of claims 7-9 and 11-13 has not been completed, pending resolution of the indefiniteness.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 10, and 19-20 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being clearly anticipated by Yoon; Youngsoo et al. (US 2021/0391407; hereinafter Yoon).
Regarding claim 1, Yoon discloses a display substrate (10; Fig 2; entire document), comprising: a substrate (100; Fig 2; ¶ [0067]), and a plurality of sub-pixels (Pm, Pa; Fig 2-3,5,9-10; ¶ [0061]), a plurality of first signal lines (horizontal voltage lines VL1b,VL2b; Fig 17; ¶ [0178-179, 0193-195,0208,0235]), and a plurality of second signal lines (vertical voltage lines VL1a,VL2a; Fig 17; ¶ [0178-179, 0193-195, 0208,0235]), provided on the substrate, wherein:
a sub-pixel of the plurality of sub-pixels comprises a pixel circuit (PC; Fig 8; ¶ [0178-179]) electrically connected with the first signal lines, the first signal lines comprise at least one initial signal line (VL1b,VL2b; Figs 10,13-20; ¶ [0208,0235]), and second signal lines comprises at least one initial connection line (VL1a,VL2a; Figs 10,13-20; ¶ [0253,0254]); the initial signal line is extended along a first direction (x-direction; Fig 17), the initial connection line is extended along a second direction (y-direction; Fig 17), and the first direction is intersected with the second direction; and
the at least one initial signal line is in a one-to-one correspondence with the at least one initial connection line (Fig 17; ¶ [0235]), and the initial signal line is electrically connected with the corresponding initial connection line (¶ [0235]).
Regarding claim 2, Yoon discloses the display substrate of claim 1, wherein the at least one initial signal line comprises a first initial signal line (VL1b; Figs 16-17) and a second initial signal line (VL2b; Figs 16-17), wherein the second initial signal line is located at a side of the first initial signal line away from the substrate (as shown in Fig 16).
Regarding claim 3, Yoon discloses the display substrate of claim 2, further comprising a plurality of reset signal lines (SL3,SL4; Figs 8,10,13,15; ¶ [0184,0186]) extending, at least partially, along the first direction (x-direction), wherein
an orthographic projection of the first initial signal line (VL1b, below SL3; Fig 15) on the substrate is located between an orthographic projection of the second initial signal line (VL2b; Fig 15) on the substrate and an orthographic projection of a reset signal line (SL3; Fig 15) on the substrate, and is not overlapped with the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the reset signal line on the substrate (as shown in Fig 15).
Regarding claim 4, Yoon discloses the display substrate of claim 2, further comprising: a plurality of light emitting signal lines (EL; Figs 3,15; ¶ [0178; 0208]) extending, at least partially, along the first direction (x-direction), wherein
an orthographic projection of the second initial signal line (VL2b, above T5; Fig 15) on the substrate is located between an orthographic projection of the first initial signal line (VL1b; Fig 15) on the substrate and an orthographic projection of a light emitting signal line on the substrate, and is not overlapped with the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the light emitting signal line on the substrate (as shown in Fig 15).
Regarding claim 5, Yoon discloses the display substrate of claim 4, wherein:
the at least one initial connection line comprises a plurality of first initial connection lines (VL1a) and a plurality of second initial connection lines (VL2a), wherein the first initial connection lines and the second initial connection lines are disposed in a same layer (¶ [0255]), the plurality of first initial connection lines are arranged along the first direction (Fig 18), and the plurality of second initial connection lines are arranged along the first direction (Fig 18);
the first initial connection lines and the second initial connection lines are alternately arranged along the first direction (Fig 18), a centerline extending along the second direction between two first initial connection lines (VL1a; Fig 18) passes through a signal body line (VL2a, being between protrusion portions VL2ap; Fig 18; ¶ [0256,0270]) of a second initial connection line (VL2a) located between the two first initial connection lines; and
a first initial connection line is electrically connected with the first initial signal line (VL1b) through a via (37; Fig 11; ¶ [0235]), and a second initial connection line is electrically connected with the second initial signal line (VL2b) through a via (43; Fig 14; ¶ [0254]).
Regarding claim 10, Yoon discloses the display substrate of claim 1, wherein pixel structures of pixel circuits of adjacent sub-pixels located in a same row are symmetrically disposed with respect to a virtual straight line extending along the second direction (see for example, PCa and PCb which have a symmetric structure about a line along VL1a; Fig 10; ¶ [0207]).
Regarding claim 19, Yoon a display apparatus (1; Figs 1-2; ¶ [0058-84]), comprising the display substrate of claim 1.
Regarding claim 20, Yoon discloses the display substrate of claim 3, further comprising: a plurality of light emitting signal lines (EL; Figs 3,15; ¶ [0178; 0208]) extending, at least partially, along the first direction (x-direction), wherein
an orthographic projection of the second initial signal line (VL2b, above T5; Fig 15) on the substrate is located between an orthographic projection of the first initial signal line (VL1b; Fig 15) on the substrate and an orthographic projection of a light emitting signal line on the substrate, and is not overlapped with the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the light emitting signal line on the substrate (as shown in Fig 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon; Youngsoo et al. (US 2021/0391407; hereinafter Yoon) in view of Wu, Zhong-hou et al. (CN-114899198-A; hereinafter Wu).
Regarding claim 14, Yoon discloses the display substrate of claim 1, further comprising: a plurality of first power supply lines (PL; Fig 3; ¶ [0095]) wherein:
the sub-pixel further comprises a light emitting device (OLED; Fig 7; ¶ [0124]), the light emitting device comprises a first electrode (121; Fig 7; ¶ [0154]), and the pixel circuit comprises an oxide transistor (TFT, where A1 may include an oxide of indium, gallium, others {¶ [0136]}; Fig 7; ¶ [0154,0134-139]).
Yoon does not disclose a plurality of planarization portions wherein:
the planarization portions are disposed between adjacent first power supply lines, and connected with the adjacent first power supply lines (to form a mesh structure; ¶ [0246]);
orthographic projections of the planarization portions on the substrate is overlapped, at least partially, with orthographic projections of a reset signal line, a first scan signal line, a second scan signal line, an active layer of the oxide transistor and the first electrode of the light emitting device on the substrate; and
at least one of the orthographic projections of the planarization portions on the substrate is overlapped, at least partially, with an orthographic projection of a first initial signal line on the substrate.
In the same field of endeavor, Wu discloses a similar display substrate comprising: a plurality of first power supply lines (204; Figs 6,9; ¶ [n0112]) and a plurality of planarization portions (203; Figs 6,9; ¶ [n0115]) wherein:
the planarization portions are disposed between adjacent first power supply lines (Fig 9; ¶ [n0112]), and connected with the adjacent first power supply lines (Fig 9; ¶ [n0112]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the power supply lines structure of Wu with the display substrate of Yoon. Considering the area of the planarization portions of Wu shown in Fig 6 and associated description, overlapping a plurality of initialization lines, scan lines, transistors, and other elements of the pixel circuit, it would have been further obvious for the combination to satisfy the further limitations of claim 14. One would have been motivated to do this in order to avoid or improve a color shift problem caused by a first electrode of a light-emitting element placed on a film layer having insufficient flatness (Wu; ¶ [n0113-115]). One would have had a reasonable expectation of success because of the similar structures and endeavors of Yoon and Wu.
Regarding claim 15, Yoon in view of Wu discloses the display substrate of claim 14, but does not disclose wherein a plurality of annular regions are formed between the plurality of first power supply lines and the plurality of planarization portions; and at least two annular regions are in different shapes.
However, it would have been obvious for a person having ordinary skill in the art at least to have tried different shapes for various portions comprising the power supply line configuration, such as by adding annular regions, in order to accommodate a particular combination of underlying structures and associated topography in order to provide the needed flatness for the first electrode of the light-emitting element. It has been held in re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) that adjusting the shape of an articles involves only routine skill in the art. See MPEP 2144.04.IV.
Regarding claim 16, Yoon in view of Wu discloses the display substrate of claim 14, comprising a display region (Yoon; DA; Figs 1,3; ¶ [0059) and a non-display region (Yoon; DPA; Figs 1,3; ¶ [0059),
wherein: the display substrate further comprises a third signal line (Yoon; 15; Fig 3; ¶ [0091,0096]) located in the non-display region,
the sub-pixels (Yoon; Pm,Pa; Figs 3,7), the first signal lines (Yoon; VL1b,VL2b; Fig 10) and the second signal lines (Yoon; VL1a,VL2a; Fig 10) are located in the display region, the third signal line comprises at least one initial power supply line (Yoon; VL; Fig 3; ¶ [0091,0096]), the initial power supply line is extended, at least partially, along the second direction (Yoon; y-direction; Fig 3); and
the at least one initial power supply line is in one-to-one correspondence with the at least one initial signal line (Yoon; VL1b,VL2b; VL including VL1a corresponds one-to-one with VL1b; ¶ [0235]), and the initial power supply line is electrically connected with the corresponding initial signal line (Yoon; ¶ [0235]).
Regarding claim 17, Yoon in view of Wu discloses the display substrate of claim 16, wherein the display region (Yoon; DA; Fig 3) comprises a first side (Yoon; upper side of MDA rectangle; Fig 3) and a second side (Yoon; lower side of MDA rectangle; Fig 3) disposed opposite to each other, and the third signal line (Yoon; 15, located on the lower side of the MDA rectangle; Fig 3) is located on at least one of the first side and the second side of the display region.
Regarding claim 18, Yoon in view of Wu discloses the display substrate of claim 15, further comprising (all cited from Yoon, except as noted): a drive structure layer (PCL; Fig 2; ¶ [0126]) disposed on the substrate, wherein:
the drive structure layer comprises a first semiconductor layer (A1 {comprising C7}, on layer 111; Fig 7 {12}; ¶ [0135-136 {0215}]), a first conductive layer (G1/G2{G7}, on layer 112; Fig 7{12}; ¶ [0135-139]), a second conductive layer (CE2, on layer 113; Fig 7; ¶ [0135,0142]), a second semiconductor layer (comprising C3; Fig 12; ¶ [0223]), a third conductive layer (G3b, on 115; Fig 12; ¶ [0227]), a fourth conductive layer (connection electrodes 172-176, on layer 116; Fig 12; ¶ [0230]) and a fifth conductive layer (DL,PL; Figs 11,12; ¶ [0246]) which are stacked in sequence;
the first conductive layer comprises (Yoon; SL1,EL,CE1, each on layer 112; Fig 7; ¶ [0216,0221]), at least, a first scan signal line (SL1), a light emitting signal line (EL), and a first plate (CE1) located in a capacitor of at least one sub-pixel;
the second conductive layer comprises (Yoon), at least, the first initial signal line (VL1b, on 113; Fig 16; ¶ [0219-220]), a first sub-reset signal line of the reset signal line (145 of SL3, comprising a portion of G4a {¶ [0228]}, on 113; Fig 12; ¶ [0225-228]), a first sub-scan signal line of the second scan signal line (143 of SL2, on 113; ¶ [0220]), and a second plate (CE2, on layer 113; Fig 7) located in the capacitor of the at least one sub-pixel;
the third conductive layer comprises, at least, a second sub-reset signal line (165 of SL3, on 115; ¶ [0225]) of the reset signal line, a second sub-scan signal line of the second scan signal line (163 of SL2, on 115; ¶ [0225]), and a second initial signal line (VL2b, on 115; Fig 16);
the fourth conductive layer comprises, at least, a first initial connection line (VL1a) and a second initial connection line (VL2a; each on 116; ¶ [0255]);
the fifth conductive layer comprises, at least, data signal lines (DL, on 117a; Fig. 11; ¶ [0197]), the first power supply lines (PL, on 117a; Fig 11), and the planarization portions (Wu; as applied to claim 14, on the same layer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lv, Lan-fen et al. (CN-115132809-A; the prior art discloses a plurality of initial signal lines which form a mesh structure);
Yang; Yuehua (US 2024/0114738; the prior art discloses a plurality of reference voltage signal lines {initial signal lines} which form a mesh structure);
Zhang; Lin et al. (US 2023/0326402; the prior art discloses a plurality of reset signal lines {initial signal lines} which form a mesh structure).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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