DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/12/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5 and 9-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANEKO (US 20200098787 A1)
With regards to claim 1, Kaneko discloses a 3D flash memory (31A-31D) comprising:
interlayer insulating films (insulating strips 32) and word lines (word lines/conductive strips 46) configured to extend in a horizontal direction and alternately stacked in a vertical direction; (see FIGS. 31A and 31C)
vertical channel structures (channel 60 and memory film 50) configured to extend through the interlayer insulating films and the word lines in the vertical direction, wherein each of the vertical channel structures includes a vertical channel pattern (channel 60) configured to extend in the vertical direction and a data storage pattern (memory film 50) configured to surround an outer wall of the vertical channel pattern; and
at least one vertical connecting pattern (connecting pattern comprising layers 52 and 54 connecting adjacent structures 60 but not including structure 60, see FIG. 31D) configured to connect the vertical channel structures to each other on a horizontal plane and extend in the vertical direction, (See FIG. 31D)
wherein each vertical connecting pattern is a complete connecting structure between the vertical channel structures, and the entirety of each vertical connecting pattern is formed of only the data storage pattern included in each of the vertical channel structures. (see FIG. 31D, where the connecting pattern is comprised only of layers 52 and 54, and is a complete structure, see also response to Arguments)
With regards to claim 2, Kaneko discloses the 3D flash memory of claim 1.
It should be noted that the limitation “wherein the at least one vertical connecting pattern is simultaneously formed with the vertical channel structures through the same process” is being interpreted as a product by process, and will not be given patentable weight (See MPEP 2113 I.)
With regards to claim 4, Kaneko discloses the 3D flash memory of claim 1, wherein the at least one vertical connecting pattern has a size smaller than a size of each of the vertical channel structures on the horizontal plane. (See FIG. 31D, where the size on at least layer 52 is less than the size of layer 60)
With regards to claim 5, Kaneko discloses the 3D flash memory of claim 1, wherein the at least one vertical connecting pattern connects the vertical channel structures to each other to divide the word lines on the horizontal plane. (See FIG. 31D)
With regards to claim 9, Kaneko discloses a 3D flash memory (31A-31D) comprising:
interlayer insulating films (insulating strips 32) and word lines (word lines/conductive strips 46) configured to extend in a horizontal direction and alternately stacked in a vertical direction; (see FIGS. 31A and 31C)
vertical channel structures (channel 60 and memory film 50) configured to extend through the interlayer insulating films and the word lines in the vertical direction, wherein each of the vertical channel structures includes a vertical channel pattern (channel 60) configured to extend in the vertical direction and a data storage pattern (memory film 50) configured to surround an outer wall of the vertical channel pattern; and
at least one separation film (connecting pattern comprising layers 52 and 54 connecting adjacent structures 60, but not including structure 60, see FIG. 31D) configured to divide each of the word lines into a plurality of word lines on a horizontal plane, (See FIG. 31D)
wherein each separation film is a complete connecting structure between the vertical channel structures, and the entirety of each vertical connecting pattern is formed of only the data storage pattern included in each of the vertical channel structures. (see FIG. 31D, where the connecting pattern is comprised only of layers 52 and 54, and is a complete structure, see also response to Arguments)
With regards to claim 10, Kaneko discloses the 3D flash memory of claim 9, wherein the at least one separation film connects vertical channel structures included in at least one row or column among the vertical channel structures on the horizontal plane. (See FIG. 31D)
With regards to claim 11, Kaneko discloses the 3D flash memory of claim 10, wherein the at least one separation film includes:
the vertical channel structures (channel 60) included in the at least one row or column; and
connecting parts (connecting portions of layers 52/54) configured to connect the vertical channel structures included in the at least one row or column on the horizontal plane. (See FIG. 31D)
With regards to claim 12, Kaneko discloses the 3D flash memory of claim 11, wherein each of the vertical channel structures included in the at least one row or column does not include the vertical channel pattern. (See FIG. 31D, where the vertical channel structure comprising the connection portion 52/54 does not include the channel pattern 60)
With regards to claim 13, Kaneko discloses the 3D flash memory of claim 9, wherein the at least one separation film has a shape in which protrusions and indentations are repeated in an extension direction on the horizontal plane to divide each of the word lines into the plurality of portions on the horizontal plane. (See FIG. 31SD, showing the protrusions and indentations of the layers 52/54 of the separation film)
With regards to claim 14, Kaneko discloses the 3D flash memory of claim 9.
It should be noted that the limitation “wherein the at least one vertical connecting pattern is simultaneously formed with the vertical channel structures through the same process” is being interpreted as a product by process, and will not be given patentable weight (See MPEP 2113 I.)
Response to Arguments
Applicant's arguments filed 06/28/2026 have been fully considered but they are not persuasive.
Applicant essentially argues that the “complete” structure of claims 1 and 9 must include the connecting pattern 62 in Kaneko.
It should be noted that the term “complete” is very broad, and it is within the broadest reasonable interpretation to state that the combination of layers 52 and 54 are “complete”, as the layers are finished being formed in FIG. 31.
Examiner recommends amending the claim language to further specify the specific structural elements necessary to overcome the current art, and to reach out to the Examiner via telephone interview before filing an amendment if necessary.
Therefore, claims 1 and 9 are properly rejected, and claims 2, 3-5 and 10-14 are rejected for at least their dependencies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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