Prosecution Insights
Last updated: April 19, 2026
Application No. 18/706,108

FLEXIBLE CIRCUIT BOARD AND PAD CONNECTING SYSTEM

Non-Final OA §102§103
Filed
Apr 30, 2024
Examiner
NORRIS, JEREMY C
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Suzhou MetaBrain Intelligent Technology Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
91%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
840 granted / 973 resolved
+18.3% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
23 currently pending
Career history
996
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
53.1%
+13.1% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 973 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 and 9-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0239532 A1 (Miyazaki). Miyazaki discloses, referring primarily to figures 7 and 8, a Flexible Printed Circuit (FPC) (100, [0040]), comprising: a pad configured to be welded to a Printed Circuit Board (PCB); wherein the pad comprises at least one signal pad layer (104) and at least one ground pad layer (106); and a signal pad area in the signal pad layer is smaller than a ground pad area in the ground pad layer ([0040]) [claim 1], wherein the signal pad area comprises at least one first elliptical via (seen in figures 7 and 8, not specifically referenced) configured for tin penetration welding of the PCB ([0047]) [claim 2], wherein an orthographic projection of the first elliptical via on a plane parallel to the signal pad layer is a line segment area formed by connecting circular endpoints with a same diameter [claim 3], wherein the ground pad area comprises at least one second elliptical via configured for tin penetration welding of the PCB (figure 7) [claim 4], wherein an aperture size of the first elliptical via is smaller than an aperture size of the second elliptical via (figure 7) [claim 5], wherein an orthographic projection of the second elliptical via on a plane parallel to the ground pad layer is a line segment area formed by connecting circular endpoints with a same diameter [claim 6], wherein the pad comprises the signal pad layer corresponding to all or a part of signal layers in the FPC, and the ground pad layer corresponding to all or a part of ground planes of the FPC [claim 9], wherein a size of the signal pad area is obtained according to requirements for signal impedance in combination with process production capacity ([0040]-[0041]) [claim 10], wherein an orthographic projection of a via configured for tin penetration welding of the PCB in the signal pad area on a plane parallel to the signal pad layer corresponding to the signal pad area is an area enclosed by two outer tangent lines of two circles with different diameters and the two circles [claim 11], wherein each via in the signal pad area in each signal pad layer corresponds to a via in the ground pad area in the ground pad layer corresponding to the signal pad layer, so that solder enters the via in the signal pad area from the via in the ground pad area during welding ([0047]) [claim 12], wherein an aperture size of a via in the signal pad area in each signal pad layer is the same as an aperture size of a via in the ground pad area in the ground pad layer corresponding to the signal pad layer (figure 8) [claim 13], wherein an aperture size of a via in the ground pad area is greater than an aperture size of the first elliptical via in the signal pad area corresponding to the ground pad area (figure 7) [claim 14]. Similarly, Miyazaki discloses, a pad connection system, comprising: a Printed Circuit Board (PCB) (1) and a Flexible Printed Circuit (FPC) (3, 100), wherein the FPC comprises a pad configured to be welded to the PCB ([0047]), the pad comprises at least one signal pad layer (104) and at least one ground pad layer (106) and a signal pad area in the signal pad layer is smaller than a ground pad area in the ground pad layer (figure 7), a circuit bard pad of the PCB is welded to the pad of the FPC [claim 15], wherein a circuit board signal pad area in a circuit board signal pad layer of the circuit board pad is welded to the signal pad area of the signal pad layer of the pad of the FPC through a via in the ground pad layer of the pad of the FPC ([0005]-[0006]) [claim 16], wherein the circuit board pad comprises at least one circuit board signal pad layer and at least one circuit board ground pad layer, wherein a circuit board signal pad area in the circuit board signal pad layer is smaller than a circuit board ground pad area in the circuit board ground pad layer ([0040]-[0041]) [claim 17], wherein the circuit board pad of the PCB comprises at least one circuit board signal pad layer corresponding to all or a part of signal layers in the PCB, and at least one circuit board ground pad layer corresponding to all or a part of ground planes of the PCB [claim 18], wherein the PCB and the FPC are welded in a manner in which a signal layer of the FPC is on top and a ground plane of the FPC is on bottom [claim 19]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 7, 8, and 20 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki. Regarding claims 7 and 8, Miyazaki discloses, the claimed invention as described above with respect to claim 1 except Miyazaki does not specifically state that under the condition that the signal pad area is a differential signal pad area, a size specification of the signal pad area is 0.8 mm* 0.25 mm [claim 7] or that under the condition that the signal pad area is a single-ended signal pad area, a size specification of the signal pad area is 0.9 mm*0.3 mm [claim 8]. However, such a modification would amount to a mere change in size of the existing parts of Miyazaki, which has been held to be within the skill of the ordinary artisan (MPEP 2144). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Miyazaki. The motivation for doing so would have been to suppress deterioration ([0041]). Additionally, regarding claim 20, Miyazaki discloses, the claimed invention as described above with respect to claim 15 except Miyazaki does not specifically state that wherein sizes of a circuit board signal pad area in a circuit board signal pad layer and a circuit board ground pad area in a circuit board ground pad layer in the circuit board pad of the PCB are set in the same manner as sizes arrangement of the signal pad area and the ground pad area in the pad of the FPC [claim 20]. However, such a modification would amount to a mere change in size of the existing parts of Miyazaki, which has been held to be within the skill of the ordinary artisan (MPEP 2144). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Miyazaki. The motivation for doing so would have been to suppress deterioration ([0041]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEREMY C. NORRIS Examiner Art Unit 2847 /JEREMY C NORRIS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Apr 30, 2024
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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LAMINATE FOR WIRING BOARD
2y 5m to grant Granted Apr 14, 2026
Patent 12604411
FLEXIBLE PRINTED CIRCUIT BOARD, IN PARTICULAR FOR CONNECTING ELECTRICAL AND/OR ELECTRONIC COMPONENTS
2y 5m to grant Granted Apr 14, 2026
Patent 12598703
WIRING CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598698
WIRING CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598693
THICK FILM PRINTED COOLER FOR IMPROVED THERMAL MANAGEMENT OF DIRECT BONDED POWER DEVICES
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
91%
With Interview (+4.4%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 973 resolved cases by this examiner. Grant probability derived from career allow rate.

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