DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/28/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2024/0179969).
Regarding claim 1, Han discloses, in at least figures 1-3 and related text, a display panel comprising a display area (AA, [57]), a first driving circuit area (area of 20, [59]) located on a first side of the display area (AA, [57]), and a fan-out wiring area (FA, [57]) located on a second side of the display area (AA, [57]);
the display panel further comprises:
a panel body comprising first gate driving circuits (20, [59]) disposed in the first driving circuit area (area of 20, [59]), one or more bonding terminals (92, [127]) disposed at a side of the fan-out wiring area (FA, [57]) away from the display area (AA, [57]), a first input signal line (one 40/50, [62]), and a second input signal line (another 40/50, [62]);
wherein the first input signal line (one 40/50, [62]) comprises a first connection terminal (40 of one 40/50, [62]) and an opposing second connection terminal (50 of one 40/50, [62]), the first connection terminal (40 of one 40/50, [62]) is electrically connected to one or more of the first gate driving circuits (20, [59]), the second connection terminal (50 of one 40/50, [62]) is electrically connected to one of the one or more bonding terminals (92, [127]), and a part of the first input signal line (one 40/50, [62]) is located in the fan-out wiring area (FA, [57]);
the second input signal line (another 40/50, [62]) comprises a third connection terminal (40 of another 40/50, [62]) and an opposing fourth connection terminal (50 of another 40/50, [62]), the third connection terminal (40 of another 40/50, [62]) is electrically connected to one or more of the first gate driving circuits (20, [59]), the fourth connection terminal (50 of another 40/50, [62]) is electrically connected to one of the one or more bonding terminals (92, [127]), and a part of the second input signal line (another 40/50, [62]) is located in the fan-out wiring area (FA, [57]);
wherein a voltage applied by the bonding terminal electrically connected to the first input signal line is the same as a voltage applied by the bonding terminal electrically connected to the second input signal line (the limitation of "a voltage applied by the bonding terminal electrically connected to the first input signal line is the same as a voltage applied by the bonding terminal electrically connected to the second input signal line" has not patentable weight because it is interpreted as operational property).
Regarding claim 11, Han discloses the display panel according to claim 1 as described above.
Han further discloses, in at least figures 1-3 and related text, the bonding terminal (92, [127]) electrically connected to the first input signal line (one 40/50, [62]) and the bonding terminal (92, [127]) electrically connected to the second input signal line (another 40/50, [62]) are different bonding terminals (92, [127]).
Regarding claim 12, Han discloses the display panel according to claim 1 as described above.
Han further discloses, in at least figures 1-3 and related text, the panel body comprises a plurality of pixel driving circuits (T, 60]) disposed in the display area (AA, [57]) and arranged in a second direction (x direction, figures) and a third direction (y direction, figures), the second direction (x direction, figures) intersects the third direction (y direction, figures), and the first gate driving circuits (left 20, [59], figures) comprises a plurality of first gate control circuits (left 20, [59], figures) disposed in the first driving circuit area (area of left 20, [59], figures) and arranged in the third direction (y direction, figures);
the panel body further comprises a plurality of first output signal lines (GL, [60]), one terminal of each of the first output signal lines (GL, [60]) being connected to one of the first gate control circuits (left 20, [59], figures), the other terminal of each of the first output signal lines (GL, [60]) being connected to a plurality of the pixel driving circuits (T, 60]) arranged in the second direction (x direction, figures), the first output signal lines (GL, [60]) being used to transmit voltage signals in the first input signal line (one 40/50, [62]) and the second input signal line (another 40/50, [62]) to the pixel driving circuits (T, 60]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han (US 2024/0179969) in view of Wang (US 2024/0021152).
Regarding claim 19, Han discloses the display panel according to claim 1 as described above.
Han does not explicitly disclose each of the pixel driving circuits comprises a driving transistor and a compensation transistor, a first electrode of the driving transistor and a first electrode of the compensation transistor are both connected to a first node, a gate of the driving transistor and a second electrode of the compensation transistor are both connected to a second node, and the first output signal line is connected to a gate of the compensation transistor.
Wang teaches, in at least figure 1 and related text, the device comprising each of the pixel driving circuits comprises a driving transistor (T5, [39]) and a compensation transistor (T2, [39]), a first electrode of the driving transistor (T5, [39]) and a first electrode of the compensation transistor (T2, [39]) are both connected to a first node, a gate of the driving transistor (T5, [39]) and a second electrode of the compensation transistor (T2, [39]) are both connected to a second node, and the first output signal line (S3, [34]) is connected to a gate of the compensation transistor (T2, [39]), for the purpose of providing a pixel circuit and a display panel to alleviate a technical problem that a pixel circuit needs to use more wires ([4]).
Han and Wang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Han to have each of the pixel driving circuits comprising a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor being both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor being both connected to a second node, and the first output signal line being connected to a gate of the compensation transistor, as taught by Wang, for the purpose of providing a pixel circuit and a display panel to alleviate a technical problem that a pixel circuit needs to use more wires ([4], Wang).
Regarding claim 19, Han in view of Wang discloses the display panel according to claim 1 as described above.
Wang further teaches, in at least figure 1 and related text, the compensation transistor (T2, [39]) is an N-type thin film transistor, for the purpose of providing a pixel circuit and a display panel to alleviate a technical problem that a pixel circuit needs to use more wires ([4]).
The claimed limitation of "a voltage applied by the bonding terminal electrically connected to the first input signal line and a voltage applied by the bonding terminal electrically connected to the second input signal line are both high potentials" has not patentable weight because it is interpreted as operational property.
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 2 that recite "the first input signal line and the second input signal line are electrically connected to same one of the one or more bonding terminals" in combination with other elements of the base claims 1 and 2.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 12, and 13 that recite "the first gate control circuits connected to the first input signal Line alternate with the first gate control circuits connected to the second input signal line in the third direction" in combination with other elements of the base claims 1, 12, and 13.
Claims 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 12, and 14 that recite "the first gate driving circuits further comprises a plurality of second gate control circuits disposed in the first driving circuit area and arranged in the third direction, the panel body further comprises a plurality of second output signal lines, and the plurality of second gate control circuits are located on one side of the plurality of first gate control circuits away from or close to the display area; one terminal of each of the second output signal lines is connected to one of the second gate control circuits, and the other terminal of each of the second output signal lines is connected to a plurality of the pixel driving circuits arranged in the second direction" in combination with other elements of the base claims 1, 12, and 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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