Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 10th, 2026 has been entered. Claims 1 and 12-21 are pending in this application. Applicant amended independent claim 1 to incorporate limitations from previously dependent claims 2-11. Claims 2-11 have been canceled.
Claim 16 has been amended to address the indefiniteness issue previously set forth in the Non-Final Office Action mailed November 17th, 2025, regarding the phrase “at the same time at a timing.” The amendment resolves the 35 USC § 112(b) rejection, which has been withdrawn.
Applicant has further added new claims 19-21. These claims have been addressed below.
Applicant’s amendments to the claims have been fully considered. The previous rejections set forth in the prior Office action have been withdrawn in light of the claim amendments and/or applicant’s arguments, which have been found persuasive with respect to the prior art previously relied upon. However, upon further consideration of the amended claims, a new ground(s) of rejection is made, as set forth below.
Response to Arguments
Applicant's arguments filed February 10th, 2026 have been fully considered but they are not persuasive.
Applicant argues that the cited references fail to teach a rail transit signal system or communication with a rail station MC. However, the teaching of a rail system is considered the intended use of the claimed invention and does not impose structural limitation. Kim (US 2010/0110900) teaches transmitting and receiving communication signals in a network (Kim, para. [0020] & para. [0022]) and is considered analogous art.
Applicant further argues that Kim does not teach the claimed modules. However, Kim’s transmitters and receivers perform the same functions as the claimed control instruction sending module and device state receiving module (Kim, para. [0020] & para. [0025]).
Regarding the data validity check module, Ethernet redundancy, and system configuration/maintenance functionality, Ma (US 2017/0195260) teaches processing circuitry and redundant LAN communication (Ma, para. [0027]), and it would have been obvious to implement these functions as connected modules.
Applicant’s arguments regarding specific frame formats, synchronization, and error-checking limitations are not persuasive, as Kim teaches packet -based communication and error detection (Kim, para. [0029] & para. [0032]), and these implementation details represent design choices.
Newly added claims containing railway-specific data and control instructions are directed to the data content and do not add structural limitations of the claimed apparatus.
The new claim teaching a “single integrated device” is also not persuasive, since Kim teaches integrated communication components (Kim, para. [0024] & para. [0053]), which represents a routine design choice.
Accordingly, the rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 12-15, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2010/0110900), in view of Hanson (US 4,481,642), further in view of Ma (US 2017/0195260) and further in view of Shibata (US 8,385,495).
Regarding claim 1, Kim teaches an FSK and LAN protocol conversion apparatus (Kim, para. [0024], lines 1-12, “The transmitters 104, 106, 108, 110, 112, 114 and 116 are any type of device capable of transmitting any type of modulated communication signal, over electrical circuit 102 without compromising the power delivering function of the electrical network 102, that includes any type of information. For example, the transmitters 104, 106, 108, 110, 112, 114 and 116 may include controllers to form packets or messages, modems to convert the messages to suitable signals through modulation [e.g., having the proper voltage levels] for transmission, and a coupling network to provide filtering and protective functions to connect any of the transmitters to the electrical interconnect backbone 102”) for a rail transit signal system, wherein the apparatus comprises:
a control instruction sending module (TC) sending control instructions to a rail station MC using FSK communication (Kim, para. [0020], lines 1-3, “signals are transmitted from a plurality of transmitters that are positioned in an electrical network”; para. [0022], lines 1-5, “In other examples, each of the plurality of transmitters receives a command signal from the single receiver. Each transmitter only transmits signals to the single receiver when the command signal has been received at the selected transmitter”); a device state receiving module (TK) receiving device states from the rail station MC using FSK communication (Kim, para. [0020], lines 5-8, “At the single receiver, the received signals are analyzed and it is determined from the analysis of the received signals whether a fault has occurred in the electrical network between transmitters and receiver”); a data validity check module (VD) connected with the control instruction sending module (TC) and the device state receiving module (TK) respectively (Kim, para. [0032], lines 7-13, “After the transmitter receives the message or packet from the receiver, this message is copied and sent back to the receiver. The comparison of the received message at the receiver against the sent message determines if there is an error in the signal, which in tum indicates that a fault exists in the wire segment between the receiver and the commanded transmitter”; Kim does not explicitly teach a data validity check module, however it does teach the function of checking the validity of data); a system configuration and maintenance module (MAN) (Kim, para. [0026], lines 1-5, “The receiver 118 communicates with a port 132 and the port 132 is coupled to an external device 134. The external device 134 may be a personal computer, display, enunciator or any other type of device that is capable of alerting a user that a fault has been detected somewhere in the network 100”; Kim does not explicitly teach the module, however it does teach an interface for monitoring and reporting the system’s status); wherein a working process of the control instruction sending module (TC) that includes: (101) acquiring information data and a check code corresponding to the information data from the data validity check module (Kim, para. [0032], lines 5-13, “The receiver sends a message or packet [e.g., a command] to a transmitter, for example, the message of FIG. 2. After the transmitter receives the message or packet from the receiver, this message is copied and sent back to the receiver. The comparison of the received message at the receiver against the sent message determines if there is an error in the signal, which in turn indicates that a fault exists in the wire segment between the receiver and the commanded transmitter”); (102) generating, by the information coding and framing sub-module, a data stream according to a frame format, the frame format including one synchronization word followed by 10 information words (Kim, para. [0029], lines 1-6, “Referring now to FIG. 2, one example of a message format for messages transmitted according to the approaches described herein is described. A message or packet 200 includes a preamble byte 202, a receiver information byte 204, a transmitter information byte 206, and 4 to m message bytes 208 where m is an integer greater than 4”; Kim does not explicitly teach 10 information words, however a specific word count is a design choice/implementation parameter); (104) converting, by the D/A conversion sub-module, the FSK modulated data and sending the converted data to the rail station MC (Kim, para. [0054], lines 2-6, “A power line modem 921 in the transmitter 900 receives the serially transmitted digital data stream from a controller 903, converts the digital data to analog data, and modulates the analog data in FSK [Frequency Shift Keying] scheme”), wherein a format of data that the control instruction sending module (TC) sends to the rail station MC is as follows: (a) a single information frame contains 28-bit information, starting with 1 bit of a word start identifier, followed by 20 bits of information bits, followed by 1 bit of a parity check bit, and followed by 6 bits of an information error tolerance code (Kim, para. [0029], lines 1-6, “Referring now to FIG. 2, one example of a message format for messages transmitted according to the approaches described herein is described. A message or packet 200 includes a preamble byte 202, a receiver information byte 204, a transmitter information byte 206, and 4 to m message bytes 208 where m is an integer greater than 4”; para. [0025], lines 18-21, “The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”; implies parity or error checking for transmitted messages which indicates the presence of some sort of ECC code or parity; Kim does not explicitly teach the exact numerical values taught in the limitation, however specific bit counts are design choices/implementation parameters); (b) 10 single information frames are spliced into 1 complete data packet, and a 28-bit synchronous information packet is added uniformly in a header, and then the obtained 308-bit packet is sent to the rail station MC through FSK communication (Kim, para. [0059], lines 1-8, “As mentioned, in one example, the group of data bytes including the preamble, identification, and actual data form a packet. In one approach, one packet is transmitted from a transmitter and reception of the same one packet made by a receiver. In one approach, the transmitter transmits the same one packet repeatedly, with a pause between two packets, until, for example, a set number of packets are sent [e.g., 956 packets]”; Kim does not explicitly teach the exact numerical values taught in the limitation, however specific bit counts are design choices/implementation parameters); and (c) each packet of data has 200 effective information bits, and a transmission cycle is 770 ms (Kim, para. [0053], lines 5-6, “The computing code manages the number of packets sent and how often the packets are sent”; Kim does not explicitly teach the exact numerical values taught in the limitation; however, specific bit counts and cycle lengths are design choices/implementation parameters); and wherein the decision decoding in (203) is specifically as follows: performing a decoding operation, and delivering information bits and check bits (Kim, para. [0029], lines 1-6, “Referring now to FIG. 2, one example of a message format for messages transmitted according to the approaches described herein is described. A message or packet 200 includes a preamble byte 202, a receiver information byte 204, a transmitter information byte 206, and 4 to m message bytes 208 where m is an integer greater than 4”) of 10 words from word 2 to word 11 to the data validity check module for processing (Kim, para. [0032], lines 7-13, “After the transmitter receives the message or packet from the receiver, this message is copied and sent back to the receiver. The comparison of the received message at the receiver against the sent message determines if there is an error in the signal, which in tum indicates that a fault exists in the wire segment between the receiver and the commanded transmitter”; para. [0044], lines 1-4, “The controller 703 at step 762 reads the stored packets 742 and 743 and makes a bit-by-bit comparison of all n data bytes against the pre-set values of the n data bytes between the packets 742 and 743”). The preamble phrase “for a rail transit signal system” is treated as non-limiting because it merely recites an intended use and does not provide essential structure or steps.
Kim fails to teach the apparatus comprising a first Ethernet redundant communication module (LAN A) connected with the data validity check module (VD); a second Ethernet redundant communication module (LAN B) connected with the data validity check module (VD); and a system configuration and maintenance module (MAN) connected with the control instruction sending module (TC), the device state receiving module (TK), the data validity check module (VD), the first Ethernet redundant communication module (LAN A), and the second Ethernet redundant communication module (LAN B), the working process of the control instruction sending module (TC) as follows: (103) performing, by the FSK modulation sub-module, FSK modulation on the generated data stream; wherein a specific process of performing, by the FSK modulation sub-module, FSK modulation on the generated data stream is as follows: an up-sampling process, a molding filtering process, a 3-stage CIC interpolation process, a phase accumulation process and an orthogonal modulation process, wherein a working process of the device state receiving module (TK) is specifically as follows: (201) receiving data from the rail station MC, converting, by the A/D conversion sub-module, the received data, and sending the converted data to the FSK demodulation sub-module; (202) performing, by the FSK demodulation sub-module, FSK demodulation on the received data; and (203) performing, by the information decoding and deframing sub-module, frame synchronization, bit synchronization and decision decoding in turn on the data obtained through the FSK demodulation, wherein a specific process of performing, by the FSK demodulation sub-module, FSK demodulation on the received data is as follows: a down-conversion process, followed by a low-pass filtering process, followed by a matching filtering process, followed by a 3-stage CIC extraction process, followed by a phase-locked loop process and followed by a baseband signal generating process, wherein the frame synchronization in (203) is specifically as follows: calculating correlation values between baseband signal samples outputted by a phase-locked loop and a synchronization sequence to find a synchronization position, wherein the bit synchronization in (203) is specifically as follows: performing the bit synchronization according to a frame synchronization position to obtain complete data of 11 words.
However, Hanson, in an analogous art, teaches the working process of the control instruction sending module (TC) as follows: (103) performing, by the FSK modulation sub-module, FSK modulation on the generated data stream (Hanson, col. 1, lines 57-60, “The low band pass filter, in this example, then shapes the clock square wave into a sine wave and transmits it, through the output multiplexer, to a low pass output filter”); wherein a specific process of performing, by the FSK modulation sub-module, FSK modulation on the generated data stream is as follows: an up-sampling process, a molding filtering process, a 3-stage CIC interpolation process, a phase accumulation process and an orthogonal modulation process (Hanson, col. 19, lines 23-34, “An integrated circuit FSK transmitter comprising: (a) clock means for providing a clock output at a desired carrier frequency; (b) sampled analog bandpass filter means having independently controlled phase response and independently controlled amplitude response, connected to the clock means, for receiving the clock output to filter and provide an FSK output signal at the desired carrier frequency; and (c) output means, connected to the bandpass filter means, for transmitting the FSK output signal”; Hanson does not explicitly teach the limitation, however Hanson teaches filtering and shaping signals for FSK modulation. Multi-stage digital filtering , interpolation, and equivalent signal processing techniques, such as CIC filtering, are well-known in digital communication systems), wherein a working process of the device state receiving module (TK) is specifically as follows: (201) receiving data from the rail station MC, converting, by the A/D conversion sub-module, the received data, and sending the converted data to the FSK demodulation sub-module; (202) performing, by the FSK demodulation sub-module, FSK demodulation on the received data; and wherein a specific process of performing, by the FSK demodulation sub-module, FSK demodulation on the received data is as follows: a down-conversion process, followed by a low-pass filtering process, followed by a matching filtering process, followed by a 3-stage CIC extraction process, followed by a phase-locked loop process and followed by a baseband signal generating process (Hanson, col. 2, lines 7-13, “The demodulator circuit has a mark filter and a space filter, each of which receives the sine wave. A full wave rectifier receives the output of the mark filter and the space filter, effectively comparing the energy output of each of these filters, with the resulting output being sent to a conversion circuit for converting the rectified output to digital data”).
Kim and Hanson are both considered to be analogous to the claimed invention because both are in the same field of digital communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Kim to incorporate the teachings of Hanson by including the functionality of performing FSK modulation and demodulation.
The suggestion/motivation for doing so would be allow for packet-based communication over FSK signals (Hanson, Abstract, lines 1-3, “An integrated circuit FSK transmitter and receiver combination form a modem for receiving and transmitting FSK signals”).
The combination of Kim in view of Hanson, taken singly or combined, fails to teach a first Ethernet redundant communication module (LAN A) connected with the data validity check module (VD); a second Ethernet redundant communication module (LAN B) connected with the data validity check module (VD); and a system configuration and maintenance module (MAN) connected with the control instruction sending module (TC), the device state receiving module (TK), the data validity check module (VD), the first Ethernet redundant communication module (LAN A), and the second Ethernet redundant communication module (LAN B); (203) performing, by the information decoding and deframing sub-module, frame synchronization, bit synchronization and decision decoding in turn on the data obtained through the FSK demodulation, and wherein the frame synchronization in (203) is specifically as follows: calculating correlation values between baseband signal samples outputted by a phase-locked loop and a synchronization sequence to find a synchronization position, wherein the bit synchronization in (203) is specifically as follows: performing the bit synchronization according to a frame synchronization position to obtain complete data of 11 words.
However, Ma, in an analogous art, teaches a first Ethernet redundant communication module (LAN A) connected with the data validity check module (VD); a second Ethernet redundant communication module (LAN B) connected with the data validity check module (VD) (Ma, para. [0027], lines 7-12, “As described in IEC 62439-3, to achieve redundancy, PRP-compatible nodes are connected to two independent LAN s having similar topology [IST-LANs], e.g. LAN_A and LAN_B in FIG. 2, through two independent physical ports [port A and port B] as doubly attached nodes obeying to PRP [DANP]”); and a system configuration and maintenance module (MAN) connected with the control instruction sending module (TC), the device state receiving module (TK), the data validity check module (VD), the first Ethernet redundant communication module (LAN A), and the second Ethernet redundant communication module (LAN B) (Ma, para. [0027], lines 1-5, “FIG. 2 illustrates in more detail the components of the PRP unit 104 and the protocol stack 106 included in or associated with the processing circuit 102 and the TX/RX circuitry 112 which implement the PRP-related functions described herein”). Ma does not explicitly teach the connection; however, it teaches a structure that interfaces with multiple communication components, such as TX/RX, protocol stack, and LAN interfaces. This structure would inherently require some sort of coordination with various communication modules.
Kim, Hanson, and Ma are all considered to be analogous to the claimed invention because they are in the same field of digital communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson to incorporate the teachings of Ma by including the functionality of two Ethernet redundant communication modules, and a central configuration/maintenance module connected to various communication modules.
The suggestion/motivation for doing so would be to provide reliable redundant Ethernet communication, and to allow for coordinated monitoring and control of various system components.
The combination of Kim in view of Hanson, and further in view of Ma, taken singly or combined, fails to teach (203) performing, by the information decoding and deframing sub-module, frame synchronization, bit synchronization and decision decoding in turn on the data obtained through the FSK demodulation, and wherein the frame synchronization in (203) is specifically as follows: calculating correlation values between baseband signal samples outputted by a phase-locked loop and a synchronization sequence to find a synchronization position, wherein the bit synchronization in (203) is specifically as follows: performing the bit synchronization according to a frame synchronization position to obtain complete data of 11 words.
However, Shibata, in an analogous art, teaches (203) performing, by the information decoding and deframing sub-module, frame synchronization, bit synchronization (Shibata, col. 5, lines 5-17, “The symbol data demodulated by the quaternary FSK symbol regeneration circuit 33 is output to a frame formation circuit 35 as a 2-bit signal having a symbol rate of 2.4 ksps, as mentioned above because the signal has a quaternary. The frame formation circuit 35 is operable, when a synchronization word pattern is detected by the synchronization-word pattern detection circuit 34, i.e., signal receiving is normally performed, as described later, to form the symbol data into a given frame, and output the frame to an audio demodulator. The correction of the symbol clock by the synchronization-word-pattern detection circuit 34 and the regeneration of the symbol data by the quaternary FSK symbol regeneration circuit 33”) and decision decoding (Shibata, col. 13, lines 25-31, “the sample value at the sample point T2 is input into a symbol determination section 335, and it is determined to which of the "00", "01", "10", "11" is most likely to correspond to an actual symbol value P estimated from the sample value at the sample point T2. A result of the determination is output to the frame formation circuit 35, as the 2 bit, 2.4 ksps signal.”) in turn on the data obtained through the FSK demodulation, and wherein the frame synchronization in (203) is specifically as follows: calculating correlation values between baseband signal samples outputted by a phase-locked loop and a synchronization sequence to find a synchronization position (Shibata, Abstract, lines 8-9, “correlation processing with respect to the sync word pattern is performed to determine a correlation value”; Fig. 7), wherein the bit synchronization in (203) is specifically as follows: performing the bit synchronization according to a frame synchronization position to obtain complete data of 11 words (Shibata, col. 11, lines 30-33, “the symbol comparator 340 is operable to provide a reset signal to the quaternary FSK symbol regeneration circuit 33 at the timing of detecting a synchronization word pattern to adjust a timing of the internal symbol clock”; col. 14, lines 28-32, “The timer 333 is configured to be forcibly initialized by the reset signal output from the symbol comparator 340 of the synchronization-word-pattern detection circuit 34 at a timing of detecting a synchronization word pattern, to restart the count operation”; Shibata does not explicitly teach the exact numerical values taught in the limitation, however specific word counts are design choices/implementation parameters).
Kim, Hanson, Ma, and Shibata are all considered to be analogous to the claimed invention because they are in the same field of digital communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson, further in view of Ma, to incorporate the teachings of Shibata by including the functionality of bit and frame synchronization.
The suggestion/motivation for doing so would be to improve synchronization accuracy in an FSK communication system.
Regarding claim 12, the combination of Kim in view of Hanson, further in view of Ma, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the data validity check module (VD) comprises: a data error tolerance code generating sub-module; and a data error tolerance code check sub-module (Kim, para. [0025], lines 18-21, “The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”; implies parity or error checking for transmitted messages which indicates the presence of some sort of ECC code or parity).
Regarding claim 13, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 12, wherein the data error tolerance code generating sub-module divides acquired instruction information into 10 words according to an MC framing manner (Kim, para. [0029], lines 1-6, “Referring now to FIG. 2, one example of a message format for messages transmitted according to the approaches described herein is described. A message or packet 200 includes a preamble byte 202, a receiver information byte 204, a transmitter information byte 206, and 4 to m message bytes 208 where m is an integer greater than 4”), generates 6-bit check bits for each word (Kim, para. [0025], lines 18-21, “The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”; the detection of errors implies the generation of error bits) by a generating polynomial according to a fixed coding rule, and then splices the information and uniformly sends the spliced information to the control instruction sending module (TC) for a framing operation (Kim, para. [0059], lines 1-8, “As mentioned, in one example, the group of data bytes including the preamble, identification, and actual data form a packet. In one approach, one packet is transmitted from a transmitter and reception of the same one packet made by a receiver. In one approach, the transmitter transmits the same one packet repeatedly, with a pause between two packets, until, for example, a set number of packets are sent [e.g., 956 packets]”). The generation of a polynomial to generate 6-bit check bits for each word are considered to be a design choice, under MPEP 2144.04.
Regarding claim 14, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 12, wherein the data error tolerance code check sub-module acquires information words and a 6-bit check code stream per information word from the device state receiving module (TK) (Kim, para. [0059], lines 1-8, “As mentioned, in one example, the group of data bytes including the preamble, identification, and actual data form a packet. In one approach, one packet is transmitted from a transmitter and reception of the same one packet made by a receiver. In one approach, the transmitter transmits the same one packet repeatedly, with a pause between two packets, until, for example, a set number of packets are sent [e.g., 956 packets]”), implements a data check operation on content of each control word and a corresponding check code according to the generating polynomial, and if the check is correct, discards the 6-bit check code and repackages 200-bit pure data and sends to the Ethernet redundant communication module (Kim, para. [0025], lines 18-21, “The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”; teaches that received data is processed to determine validity or fault), and if the check is not correct, sends an all-zero packet to the Ethernet redundant communication module and sets an identification bit to identify a data check error (Kim, para. [0045], lines 6-16, “If the answer is affirmative, execution continues at step 768 where a comparison is made with a threshold 770. If the number of erred packets exceeds the threshold, a result 772 is formed as a fault [e.g., "1"] or no-fault [e.g., "0"] result of a particular transmitter as in the table of FIG. 3. The final decision on fault determination using the table [stored in memory] is made and communicated to one or more of a port 750 [for display on an enunciator 751], a communication port 752 [for presentation on a display 753] and/or port 754 [for display on a personal computer 755]”). The reference does not teach a 6-bit check code generated by a polynomial nor does it teach an all-zero packet, however these are considered to be design choices/optimizations, according to MPEP 2144.04.
Regarding claim 15, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the first Ethernet redundant communication module (LAN A) and the second Ethernet redundant communication module (LAN B) are two completely independent modules, each of which has two physical connections with a redundant red and blue Ethernet (Ma, para. [0027], lines 7-12, “As described in IEC 62439-3, to achieve redundancy, PRP-compatible nodes are connected to two independent LAN s having similar topology [IST-LANs], e.g. LAN_A and LAN_B in FIG. 2, through two independent physical ports [port A and port B] as doubly attached nodes obeying to PRP [DANP]”), so as to ensure that two redundant communication channels are still maintained with an ATS system of a control center in a case of a single module fault (Ma, para. [004], lines 8-11, “Both redundancy protocols can overcome failure of a link or a switch in a network with zero switchover time, while enabling clock synchronization according to IEEE 1588 (v2)”); and the FSK and LAN protocol conversion apparatus maintains 4 independent IP continuous communications with an ATS gateway computer at the same time (Ma, para. [0027], lines 16-21, “Two such PRP-compatible nodes DANP1, DANP2 are shown in FIG. 2, where each pair of ports for the same node share the same MAC address, but operate in parallel and are attached to the same upper layers of the protocol stack 106 e.g. through a link redundancy entity (LRE) embedded in the data link layer”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson to incorporate the teachings of Ma by including the functionality of having redundant dual-LAN architecture.
The suggestion/motivation for doing so would be to overcome link or switch failure in a network, with zero switchover time (Ma, para. [0004], lines 8-11, “Both redundancy protocols can overcome failure of a link or a switch in a network with zero switchover time, while enabling clock synchronization according to IEEE 1588 [v2]”).
Regarding claim 18, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the apparatus further comprises an external interface which specifically comprises: 4 mutually independent Ethernet interfaces (Ma, Fig. 2 teaches PRP nodes connected to two independent LANs through two independent physical ports, and separate link redundancy entities) with an ATS gateway of a control center (Ma, para. [0024], lines 6-11, “The intelligent electronic device communicates with a remote supervisory control and data acquisition [SCADA] system or a centralized protection and control [CPC] system that interfaces with the power generation, transmission or distribution system”); and two mutually independent FSK communication interfaces with a station MC cabinet (Hanson teaches an FSK modem with separate FSK receiver and transmitter portions).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson to incorporate the teachings of Ma by including the functionality of having 4 independent Ethernet interfaces with a control center.
The suggestion/motivation for doing so would be to overcome link or switch failure in a network, with zero switchover time (Ma, para. [0004], lines 8-11, “Both redundancy protocols can overcome failure of a link or a switch in a network with zero switchover time, while enabling clock synchronization according to IEEE 1588 [v2]”).
Regarding claim 19, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the device state receiving module (TK) is configured to receive, from the rail station MC (Kim, Abstract, lines 4-7, “At the single receiver, the received signals are analyzed and a determination from the analyzing the received signals is made as to whether a fault has occurred in the electrical network”; para. [0025], lines 14-21, “The modem in the receiver accepts the modulated signal via the coupling network sent from the transmitters, demodulates the signals into a digital byte format, and sends the digital data to its controller. The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”), a relay interlocking variable state collected by a collection board inside a cabinet of the rail station MC via a hard wire connection, the relay interlocking variable state includes an occupation or clearance state of a track circuit, a left or right direction of a switch, a red or white or green state of a signal, an occupation or clearance state of a maintenance pit (Kim, para. [0032], lines 9-13, “The comparison of the received message at the receiver against the sent message determines if there is an error in the signal, which in tum indicates that a fault exists in the wire segment between the receiver and the commanded transmitter”; Kim does not explicitly teach the limitation, however the determination of a fault serves as status indicators, which are types of system state data), wherein the device state receiving module (TK) is further configured to receive, from the rail station MC, an activation or cancellation state of an outdoor platform train detention device, and an activation or cancellation of a track section initialization (Kim, para. [0025], lines 18-21, “The receiver controller processes the signals for data errors or mismatch to determine whether a fault has been detected or the likelihood that a fault has been detected and/or the possible location of faults”), wherein the FSK and LAN protocol conversion apparatus is configured to process received state information (Kim, para. [0025], line 18, “The receiver controller processes the signals…”) and send the processed information to a control center (Kim, para. [0026], lines 1-2, “The receiver 118 communicates with a port 132 and the port 132 is coupled to an external device 134”) through a redundant Ethernet network (Ma, para. [0027], lines 7-12, “As described in IEC 62439-3, to achieve redundancy, PRP-compatible nodes are connected to two independent LAN s having similar topology [IST-LANs], e.g. LAN_A and LAN_B in FIG. 2, through two independent physical ports [port A and port B] as doubly attached nodes obeying to PRP [DANP]”). Kim nor Ma does not explicitly teach the limitations, specifically the claimed relay interlocking variable states including track occupancy, switch direction, signal states, and other railway-specific parameters. However, these merely represent system state information types and do not teach additional structural limitations.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson to incorporate the teachings of Ma by including the functionality of a redundant Ethernet network.
The suggestion/motivation for doing so would be to provide reliable redundant Ethernet communication.
Regarding claim 20, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 19, wherein a communication interface is configured to, based on the redundant Ethernet network (Ma, para. [0027], lines 7-12, “As described in IEC 62439-3, to achieve redundancy, PRP-compatible nodes are connected to two independent LAN s having similar topology [IST-LANs], e.g. LAN_A and LAN_B in FIG. 2, through two independent physical ports [port A and port B] as doubly attached nodes obeying to PRP [DANP]”), periodically receive system control instructions (Kim, para. [0022], lines 1-2, “each of the plurality of transmitters receives a command signal from the single receiver”; para. [0059], lines 5-8, “the transmitter transmits the same one packet repeatedly, with a pause between two packets, until, for example, a set number of packets are sent [e.g., 956 packets]”), wherein the system control instructions include route establishment or cancellation, platform train detention device activation or cancellation instructions, train interval operation level selection, and terminal platform departure time indication, wherein the train interval operation level selection includes normal, acceleration 1, acceleration 2, slow-running mode, and rainy-day mode (Kim, para. [0029], lines 3-6, “A message or packet 200 includes a preamble byte 202, a receiver information byte 204, a transmitter information byte 206, and 4 to m message bytes 208 where m is an integer greater than 4”; Kim does not explicitly teach the limitation, however the packet data it teaches can include different types of command data), wherein the FSK and LAN protocol conversion apparatus is configured to process the system control instructions (Kim, para. [0025], line 18, “The receiver controller processes the signals…”) and deliver the processed instructions to the rail station MC (Kim teaches signals being transmitted to a plurality of transmitters, which equates to sending instructions). Kim nor Ma does not explicitly teach the limitations, specifically the claimed system control instructions, such as route establishment, platform device activation, and operation modes. However, these instructions merely represent particular control data types and do not teach additional structural limitations.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson to incorporate the teachings of Ma by including the functionality of a redundant Ethernet network.
The suggestion/motivation for doing so would be to provide reliable redundant Ethernet communication.
Regarding claim 21, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the FSK and LAN protocol conversion apparatus is a single integrated device (Kim, para. [0024], lines 6-12, “the transmitters 104, 106, 108, 110, 112, 114 and 116 may include controllers… modems… and a coupling network…”; para. [0053], lines 1-2, “The transmitter 802 includes the power line modem 804 and the controller 805”). Kim teaches multiple components within a single device.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hanson, further in view of Ma, and further in view of Shibata, as applied to claim 15 above, and further in view of Silverman et al. (US 7,724,702), hereinafter Silverman.
Regarding claim 16, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 15, wherein read and write operations of the first Ethernet redundant communication module (LAN A) and the second Ethernet redundant communication module (LAN B) are separated (Ma, para. [0027], lines 7-12, “13. As described in IEC 62439-3, to achieve redundancy, PRP-compatible nodes are connected to two independent LAN s having similar topology [IST-LANs], e.g. LAN_A and LAN_B in FIG. 2, through two independent physical ports [port A and port B] as doubly attached nodes obeying to PRP [DANP]”; para. [0029], lines 1-3, “The LRE duplicates the data frame received from the upper layers, and appends a redundancy check trailer [RCT] to each duplicated data frame”; the reference teaches two physically separate network paths [LAN A and LAN B] and duplication of data frames, with each path able to perform separate operations), and an ATS instruction is delivered to the MC to ensure the uniqueness of an MC write operation (Ma, para. [0031], lines 1-5, “The two PRP frames travel through LAN_A and LAN_B with different delays and, ideally, both reach the destination node DANP2. The receiving node DANP2 consumes the first PRP frame and discards the second one [if it arrives]”; teaches only one frame is processed, which equates to ensuring the uniqueness of an MC write operation), and the remaining 3 IPs only feed back an MC state to the ATS in response to an ATS read request (Kim, para. [0039], lines 7-12, “the receiver compares the received message to the expected message and determines that a fault exists if there is a mismatch. When a mismatch exists, a potential fault may exist in the portion of the network associated with the transmitter that sent the message”).
The combination of Kim in view of Hanson, further in view of Ma, taken singly or combined, fails to teach at a timing among 4 IPs, only one master IP reads and writes.
However, Silverman, in an analogous art, teaches at a timing among 4 IPs, only one master IP reads and writes (Silverman, col. 10, lines 5-13, “The scheduler computes the most effective utilization of time sharing between the lower MAC engines and the radio and programs the controller with this optimized schedule. The interface between the controller and lower MAC engines is controlled by the controller which functions as a master to the lower MAC engines, instructing the lower MAC engines when they have access to the radio and for how long based on its programming by the scheduler”; teaches a controller acting as a master that sends instruction to parallel communication modules, e.g. the lower MAC engines).
Kim, Hanson, Ma, Shibata, and Silverman are all considered to be analogous to the claimed invention because they are in the same field of digital communication systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, to incorporate the teachings of Silverman by including the functionality of one master IP that read and writes at the same time.
The suggestion/motivation for doing so would be to ensure that there are no scheduling conflicts among the IPs (Silverman, col. 10, lines 5-13, “The scheduler computes the most effective utilization of time sharing between the lower MAC engines and the radio and programs the controller with this optimized schedule. The interface between the controller and lower MAC engines is controlled by the controller which functions as a master to the lower MAC engines, instructing the lower MAC engines when they have access to the radio and for how long based on its programming by the scheduler”).
Regarding claim 17, the combination of Kim in view of Hanson, further in view of Ma, and further in view of Shibata, teaches the FSK and LAN protocol conversion apparatus for a rail transit signal system according to claim 1, wherein the system configuration and maintenance module (MAN) is used to refresh an internal component of the apparatus, and the MAN connects diagnostic software of a PC through a network or a serial port to monitor an input or output interface of each module in real time (Kim, para. [0026], lines 1-8, “The receiver 118 communicates with a port 132 and the port 132 is coupled to an external device 134. The external device 134 may be a personal computer, display, enunciator or any other type of device that is capable of alerting a user that a fault has been detected somewhere in the network 100. The location of faults and message error rate calculated for the location may also be displayed to give the severity [likelihood] or status of the fault progress”), and bypasses an ATS input to force the interface to output specific control code bits (Kim, para. [0054], lines 8-11, “The modulated signal is amplified by an amplifier 922 and sent through a coupler 923, which sends the modulated signals and blocks all other signals outside the frequency band, to the electrical wires 910 and 911”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ryan (US 11,962,443) teaches FSK-based communication including modulation and demodulation of digital data signals.
Mizuno (US 2008/0074181) teaches synchronization and signal processing techniques in communication systems.
Zehavi et al. (US 7,239,675) teaches network communication and data transmission in Ethernet-based systems.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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