Prosecution Insights
Last updated: August 17, 2026
Application No. 18/707,256

DISPLAY SUBSTRATE AND DISPLAY DEVICE

Non-Final OA §103
Filed
May 03, 2024
Priority
Nov 05, 2021 — CN 202122705798.8 +1 more
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
617 granted / 676 resolved
+23.3% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
710
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
58.9%
+18.9% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 676 resolved cases

Office Action

§103
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 36 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Koide et al. (US 2021/0255514 A1) in view of Moon et al. (US 2020/0295310 A1). Regarding independent claim 1: Koide teaches (e.g., Figs. 1-8) a display substrate, comprising: a base substrate ([0030]: SUB1) comprising a display area ([0021]-[0023]: DA) and a peripheral area ([0021]-[0025]: BE); a light-shielding layer ([0054]: 67) on the base substrate; a gate layer ([0032] and [0054]-[0056]: 12) at a side of the light-shielding layer away from the base substrate; and a source-drain metal layer ([0057]: 62/63) at a side of the gate layer away from the light-shielding layer (67), wherein the display area (DA) comprises a plurality of signal lines ([0028], [0030] and [0032]-[0033]: SL), the peripheral area (BE) comprises a lead wire region ([0027]-[0028] and [0049]-[0050]: LA region) and a bonding region ([0027]-[0028], [0049]-[0050] and [0082]-[0083]: region including wiring region LA and terminals T1 region; this interfacial region is used for bonding the wires and the terminal; described as coupling the terminals and the wiring; thus, this meets the claim limitation of bonding region), the lead wire region comprises a plurality of lead wires ([0049]-[0050] and [0066]-[0068]: LA1 and LA2), the plurality of lead wires (LA1 and LA2) are connected to the plurality of signal lines (Fig. 5; SL) and extend, in the lead wire region, to the bonding region. Koide does not expressly teach that the plurality of lead wires are distributed in the light-shielding layer, the gate layer, and the source-drain metal layer. Moon teaches (e.g., Figs. 1-4) a display substrate comprising a plurality of lead wires ([0124]-[0125]: W1,W2 and W3), a light-shielding layer ([0091]: layer of BSM; the BSM functions as a light-shielding; it is described as “prevent external light from reaching the semiconductor layer A1”), a gate layer ([0094]:layer of G1) and a source-drain metal layer ([0072] and [0097]: S1/D1); Moon further teaches that the plurality of lead wires ([0124]-[0125]: W1,W2 and W3) are distributed in the light-shielding layer ([0091]: layer of BSM; the BSM functions as a light-shielding; it is described as “prevent external light from reaching the semiconductor layer A1”), the gate layer ([0094]:layer of G1), and the source-drain metal layer ([0072] and [0097]: S1/D1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Koide, the plurality of lead wires being distributed in the light-shielding layer, the gate layer, and the source-drain metal layer, as taught by Moon, for the benefits of increasing wiring density and at the same time avoiding breaking wires or open-circuits in long wires during operation and transportation. Regarding claim 36: Koide teaches the claim limitation of the display substrate according to claim 1, on which this claim depends, wherein adjacent two lead wires in the plurality of lead wires (LA1 and LA2) at least partially overlap with each other (Figs. 5-8). Regarding claim 39: Koide teaches the claim limitation of the display substrate according to claim 1, on which this claim depends, comprising the display substrate according to claim 1, as taught in claim 1. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Koide et al. (US 2021/0255514 A1) in view of Moon et al. (US 2020/0295310 A1) as applied above and further in view of Kurashima (US 2006/0286698 A1). Regarding claim 15: Koide teaches the claim limitation of the display substrate according to claim 1, on which this claim depends. Koide does not expressly teach that a square resistance of the light-shielding layer is less than 1Ω/square. Kurashima teaches a display substrate comprising light-shielding layer ([0081]: 11a); Kurashima further teaches that a square resistance of the light-shielding layer is less than 1Ω/square ([0081]: titanium has a square resistance less than 1Ω/square; it is assumed that the titanium is pure titanium, not alloy or impurities). It is noted that titanium is an art recognized material used as light-shield material for its suitability. Applicant is reminded that using a material known in the art for its recognized suitability for an intended purpose establishes a prima facie obviousness determination; e.g., in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.) MPEP 2144.07. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Koide, a light shield material having a square resistance being less than 1Ω/square, such as the light-shielding layer made of titanium, as taught by Kurashima, for the following benefits: it is a relatively good conductor compared to many metals and its durability. Allowable Subject Matter Claims 2-6, 9-11, 13-14, 17, 20-21, 23 and 34-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display substrate comprising: “wherein the plurality of lead wires comprise a plurality of composite lead wires, each of the plurality of composite lead wires comprises at least two conductive segments electrically connected with each other, and the at least two conductive segments of a same composite lead wire are located in different conductive layers selected from the light-shielding layer, the gate layer, and the source-drain metal layer”. Claims 3-6, 9-11 and 13 depend from claim 2, and therefore, are allowable for the same reason as claim 2. Regarding claim 14: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display substrate comprising: “wherein the plurality of lead wires comprise a second single-layer lead wire, a third single-layer lead wire, and a fourth single-layer lead wire; the second single-layer lead wire is located in the source-drain metal layer, the third single-layer lead wire is located in the gate layer, and the fourth single-layer lead wire is located in the light-shielding layer”. Regarding claim 17: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display substrate comprising: “wherein the light-shielding layer comprises a first metal layer and a second metal layer arranged in a stacked manner, and a conductivity of the second metal layer is greater than a conductivity of the first metal layer”. Claims 20 and 23 depend from claim 17, and therefore, are allowable for the same reason as claim 17. Regarding claim 21: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display substrate comprising: “wherein the light-shielding layer comprises a shading structure in the display area, and the display substrate further comprises an active layer at a side of the shading structure away from the base substrate; an edge of the shading structure comprises a slope, and a ratio of a length of the slope to an average grain size of the active layer is in a range of 0.5-1.6 or, the light-shielding layer comprises a shading structure in the display area, an edge of the shading structure comprises a slope, and a slope angle between the slope and a surface of the base substrate is in a range of 30-70 degrees”. Claim 34 depends from claim 21, and therefore, is allowable for the same reason as claim 21. Regarding claim 35: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display substrate comprising: “wherein a spacing between adjacent two lead wires in the plurality of lead wires is less than a width of each lead wire”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
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Prosecution Timeline

May 03, 2024
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
95%
With Interview (+4.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 676 resolved cases by this examiner. Grant probability derived from career allowance rate.

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