DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/03/2026 have been fully considered but they are not persuasive in view of new grounds of rejection.
The Applicant contends that newly amended language “the first signal to be sent via a read bus that receives read data from the memory device" is not taught by the prior art of record.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The Examiner would like to point out Weiss teaches that when the syndrome buffer (ES-BUF) is full, the control part (ST) generates a signal (FIL) to interrupt the read operation (Col. 5, lines 1-7). While Weiss describes the functional interruption, Taylor provides the specific implementation of transmitting status signals (like a full flag) over the existing **Read/Write control bus** (Taylor, Fig. 10A). In Taylor, the bus used for the signal is the same one (or part of the same interface) that handles the data transfer. In Weiss, the error information is generated *from* the read process, so stopping the read bus (Taylor's method) is the most direct way to stop the generation of error information (Weiss's goal).
The Applicant contends, “Furthermore, the Office Action does not articulate a reasoned explanation grounded in the teachings of the cited references as to why one of ordinary skill in the art would have modified Weiss so that its FIL signal is transmitted via the read bus that receives read data from the memory device.”
The Examiner would like to point out that a person of ordinary skill in the art would find it obvious to communicate the "buffer full" status via the existing read bus (as taught by Taylor) to avoid the overhead of dedicated extra wiring. Using the read bus to carry the "stop" signal ensures that the source of the data (the memory device) is throttled immediately at the interface, preventing the exact overflow condition Weiss seeks to avoid. It would have been obvious to a person of ordinary skill in the art at the time of the invention to use the bus signaling architecture of Taylor in the controller of Weiss. This combination is motivated by the need to provide real-time feedback to the memory device using existing interface lines (the read bus), thereby reducing pin count and complexity while achieving the overflow protection taught by Weiss.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7, 21-25 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weiss; Eckardt et al. (US 4897840 A, (hereafter referred to as Weiss) and Taylor; Craig (US 6172927 B1, hereafter referred to as Taylor).
Rejection of claims 1 and 21:
Weiss teaches A controller device (Figures 1-3 and column 3, line 4 to column 5, line 7 in Weiss teaches a controller device/disk storage controller CONT connected to a data processing system SYS via a standardized interface IPI3 and connected to a memory/storage device via standardized interface IPI2; the controller device/disk storage controller CONT comprises a buffer/buffer memory ES-BUF, a protection correction means ECU in the control part ST) comprising: error detection logic to detect an error in a read operation associated with a memory device coupled to the controller device (Figures 1-3 and column 3, line 4 to column 4, line 11 in Weiss teaches the protection correction means ECU comprises error detection logic/error syndrome generator ES-GEN to detect/check for an error in a read operation associated with a memory device/storage device coupled to the controller device/disk storage controller CONT); a buffer to store error information associated with the error (Figures 1-3 and column 3, line 4 to column 5, line 7 in Weiss teaches the controller device/disk storage controller CONT comprises a buffer/buffer memory BUF to store error information/error syndrome ES associated with the error); and buffer control logic to generate and output a first signal responsive to the buffer being full (Figures 1-3 and column 3, line 4 to column 5, line 7 in Weiss teaches buffer control logic/control part ST to generate and output a first signal/FIL responsive to the buffer being full/filled). The Examiner would like to point out that previous prior art Weiss teaches in column 5 lines 1-7 that a first signal/FIL is used to interrupt the read operation to prevent subsequent error syndromes from being stored to ES-BUF syndrome buffer.
Figures 1 and 10A in Taylor; in an analogous art, teaches that a full flag/status indicator is provided on the read/write control bus. Hence, new grounds of rejection in combination with Weiss teach newly amended language in claims 1 and 21.
The Examiner would like to point out Weiss teaches that when the syndrome buffer (ES-BUF) is full, the control part (ST) generates a signal (FIL) to interrupt the read operation (Col. 5, lines 1-7). While Weiss describes the functional interruption, Taylor provides the specific implementation of transmitting status signals (like a full flag) over the existing **Read/Write control bus** (Taylor, Fig. 10A). In Taylor, the bus used for the signal is the same one (or part of the same interface) that handles the data transfer. In Weiss, the error information is generated *from* the read process, so stopping the read bus (Taylor's method) is the most direct way to stop the generation of error information (Weiss's goal).
The Examiner would like to point out that a person of ordinary skill in the art would find it obvious to communicate the "buffer full" status via the existing read bus (as taught by Taylor) to avoid the overhead of dedicated extra wiring. Using the read bus to carry the "stop" signal ensures that the source of the data (the memory device) is throttled immediately at the interface, preventing the exact overflow condition Weiss seeks to avoid. It would have been obvious to a person of ordinary skill in the art at the time of the invention to use the bus signaling architecture of Taylor in the controller of Weiss. This combination is motivated by the need to provide real-time feedback to the memory device using existing interface lines (the read bus), thereby reducing pin count and complexity while achieving the overflow protection taught by Weiss.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Weiss with the teachings of Taylor by including use of a read bus for providing a flag indicating that a buffer is full to prevent overwriting of the buffer. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of a read bus for providing a flag indicating that a buffer is full to prevent overwriting of the buffer would have provided notification to prevent overriding to a buffer (column 2, lines 23-39 in Taylor).
Rejection of claims 2 and 22:
Figures 1-3 and column 3, line 4 column 5, line 7 in Weiss clearly suggests wherein buffer control logic/control part ST is to generate an output a se2cond signal/ERR2 responsive to the buffer satisfying a field condition that is le2ss than the buffer being full. Note: since the second signal/ERR2 indicates that one error syndrome ES is stored, it also clearly indicates that the buffer was not full at the time the storage.
Rejection of claims 3-4 and 23-24:
the Applicant’s specification teaches that a back pressure signal is a signal to block read responses and data interrupt signal can trigger a read operation to read error information. Figures 1-3 and column 3, line 4 column 5, line 7 in Weiss teaches that FIL signal is used to interrupt the ongoing read operation and that the ERR2 signal is used to initiate a transfer/read operation. Note: when the ERR2 is asserted transfer out of the buffer is initiated, which indicates a higher priority.
Rejection of claims 5 and 25:
Figures 1-3 and column 3, line 4 column 5, line 7 in Weiss teaches that buffer memory ES-GEN is a FIFO.
Rejection of claims 7 and 27:
Figures 1-3 and column 3, line 4 column 5, line 7 in Weiss clearly suggest control part ST comprises matching logic to output, to the buffer, an identifier R of the read operation, and a physical address CNT of the read operation, wherein the error detection logic is an error correction code (ECC) engine, wherein the ECC engine is to: detect the error from read data; output an error signal ERR1/ERR2 to the matching logic; and output, to the buffer, the error information/error syndrome ES associated with the error concurrently with the identifier R and the physical address CNT being output by the matching logic.
Claim(s) 6 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weiss; Eckardt et al. (US 4897840 A, (hereafter referred to as Weiss), Taylor; Craig (US 6172927 B1, hereafter referred to as Taylor) and van Erickson; Evan Lawrence et al. (US 20160306922 A1, hereafter referred to as Erickson).
Rejection of claims 6 and 26:
Erickson, in an analogous art, teaches the use of a Cache-Coherent interconnect protocol, such as, CXL protocol.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Weiss and Taylor with the teachings of Erickson by including use of a Cache-Coherent interconnect protocol, such as, CXL protocol. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of a Cache-Coherent interconnect protocol, such as, CXL protocol would have provided coherency, simplification of software stacks and maintain compatibility with existing standards (paragraph [0054] on page 7 of Erickson).
Claim(s) 9 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weiss; Eckardt et al. (US 4897840 A, (hereafter referred to as Weiss), Taylor; Craig (US 6172927 B1, hereafter referred to as Taylor) and van Meaney; Patrick J. et al. (US 20160306922 A1, hereafter referred to as Meaney).
Rejection of claims 9 and 29:
Meaney, in an analogous art, teaches the use of ECC error detection to detect word line faults (paragraph [0060] on page 4 of Meaney).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Weiss and Taylor with the teachings of Meaney by including use of detecting, using the error detection logic, a plurality of errors caused by a wordline fault in the memory device. This modification would have been obvious to one o Pordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of detecting, using the error detection logic, a plurality of errors caused by a wordline fault in the memory device would have provided a means for flagging word line failures (paragraph [0060] on page 4 of Meaney).
Allowable Subject Matter
Claims 8 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: claims 8 and 28 are indicated as having allowable subject matter since they depend from respective claims 1, 7, 21 and 27 and since dependent claims inherit all the limitations of the claims from which they depend and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20110191637 A1 is directed to a method and apparatus for optimizing data transfer rates for reliable communications; and, is a good teaching reference.
US 4485470 A is directed to is directed to a method and apparatus for maintaining fault-tolerant communications in an interface used for providing parallel to seroconversion between a time division multiplexing bus in a data terminal interface; and, is a good teaching reference.
US 5276662 A is directed to an error detection means for detecting errors in data transmitted from a disc to the buffer segment and providing an error signal indicating of the transfer of a sector containing errors to the buffer segment; and means for correcting data sectors containing errors in the buffer; wherein the buffer manager further comprises a transparent latch connected to the disc pointer means for storing said indication of the number of sectors that have been transferred between the disc and the buffer in response to an error signal received from the error detection means; and wherein the pause generation means is further characterized as a means for comparing the indication of the number of sectors stored in the transparent latch to the indication of the number of sectors transferred between the host and the buffer and transmitting a host pause signal to the transfer coordinating means at such times that the number indications stored by the transparent latch is equal to the indication of the number of sectors transferred between the host and the buffer; and, is a good 103 reference that could possibly be used in a future rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112
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