DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 10-11, 17-20, and 22-28 are rejected under 35 U.S.C. 103 as being unpatentable over Avci et al. (U.S. Patent No. 9,741,832) in view of Lukyanchuk et al. (U.S. Patent No. 12,191,355).
Regarding to claim 1, Avci teaches a structure comprising: a top gate electrode (Fig. 2c, element 104; column 5, lines 13-16) and a bottom gate electrode (Fig. 2c, element 105; column 5, lines 13-16), a channel layer formed from a channel material with a band gap modulable by electric field (Fig. 2c, element 103; column 4, lines 57-61), the channel layer being electrically insulated from the top gate electrode and the bottom gate electrode (Fig. 2c, insulated by dielectric layers 106).
Avci does not explicitly disclose the channel layer being located adjacent to at least one layer of a negative capacitance material.
Lukyanchuk discloses a channel layer being located adjacent to at least one layer of a negative capacitance material (Fig. 2a, column 11, lines 7-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Avci in view of Lukyanchuk to locate at least one layer of a negative capacitance material adjacent to the channel layer in order to reduce power dissipation.
Regarding to claim 2, Avci teaches a structure comprising:
a top gate electrode (Fig. 2c, element 104; column 5, lines 13-16) and a bottom gate electrode (Fig. 2, element 105; column 5, lines 13-16),
a planar channel layer located between the top gate electrode and the bottom gate electrode (Fig. 2c, element 103; column 4, lines 1-6), the planar channel layer being separated from the top gate electrode by a first insulating layer and separated from the bottom gate electrode by a second insulating layer (Fig. 2c, insulated by dielectric layers 106);
wherein the planar channel layer is formed from a channel material with a band gap modulable by electric field (column 4, lines 58-61);
Avci does not explicitly disclose at least one of the first insulating layer and the second insulating layer are formed from a negative capacitance material.
Lukyanchuk discloses at least one of insulating layer insulating layers formed from a negative capacitance material (Fig. 2a, column 11, lines 7-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Avci in view of Lukyanchuk to form at least one of the first insulating layer and the second insulating layer from a negative capacitance material to reduce power dissipation.
Regarding to claim 3, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to form both of the first insulating layer and the second insulating layers from the ferroelectric material in order to further reduce power dissipation, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (CA7 1977).
Regarding to claim 5, Avci teaches the first insulating layer and the second insulating layer are each in physical contact with the planar channel layer, the first insulating layer being arranged on a first side of the planar channel layer and the second insulating layer being arranged on a second side of the planar channel layer (Fig. 2c).
Regarding to claim 6, Avci teaches the top gate and the bottom gate are operable independently of one another (Fig. 2c).
Regarding to claim 7, Avci teaches the structure further comprises a source electrode in electrical contact with the channel layer (Fig, 2c, element 101), and a drain electrode spaced apart from the source electrode and in electrical contact with the channel layer (Fig, 2c, element 102).
Regarding to claim 10, Avci teaches the top gate electrode and the bottom gate electrode are configured to apply an electric field across the channel layer in a direction perpendicular to a plane of the channel layer (Fig. 2c, column 7, lines 47-51).
Regarding to claim 11, Avci teaches the channel material is selected from the group consisting of few-layer graphene, a two-dimensional semiconductor, or a topological material (column 8, lines 45-48).
Regarding to claim 17, Avci teaches the planar channel layer is in the form of a thin film having a thickness of 5 nm to 15 nm (column 9, lines 20-21). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the thin film having a thickness of less than 10 nm in order to obtain desired current flow, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 18, Avci teaches the structure is a field effect transistor or a component thereof (column 7, lines 65-67).
Regarding to claim 19, Avci teaches applying or modulating a gate voltage to the top gate electrode and/or the bottom gate electrode to generate or vary an electric field across the channel layer in a direction perpendicular to a plane of the channel layer to alter the bandgap of the channel material in the channel layer (column 5, lines 3-7).
Regarding to claim 20, Avci teaches altering the bandgap of the channel layer further comprises switching the channel material between a trivial state and a non-trivial or topological state (column 4, lines 57-62).
Regarding to claim 22, Avci teaches an electrical device comprising the structure according to claim 1 (column 3, lines 24-26).
Regarding to claim 23, Avci teaches the top gate and the bottom gate are operable independently of one another (Fig. 2c).
Regarding to claim 24, Avci teaches the structure further comprises a source electrode in electrical contact with the channel layer (Fig. 2c, element 101), and a drain electrode spaced apart from the source electrode and in electrical contact with the channel layer (Fig. 2c, element 102).
Regarding to claim 25, Avci teaches the top gate electrode and the bottom gate electrode are configured to apply an electric field across the channel layer in a direction perpendicular to a plane of the channel layer (Fig. 2c, column 7, lines 47-51).
Regarding to claim 26, Avci teaches the channel material is selected from the group consisting of few-layer graphene, a two-dimensional semiconductor, or a topological material (column 8, lines 45-48).
Regarding to claim 27, Avci teaches the structure is a field effect transistor or a component thereof (column 7, lines 65-67).
Regarding to claim 28, Avci teaches an electrical device comprising the structure according to claim 2 (column 3, lines 24-26).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 4, the prior art fails to anticipate or render obvious the claimed limitations including “the channel material exhibits positive capacitance, and the combined capacitance of the channel layer, the first insulating layer, and second insulating layer is greater than 0” in combination with the limitations of claim 2 and the rest of limitations recited in claim 4.
Pertinent Art
For the benefits of the Applicant, US-11114564-B2, US-12588250-B2, and US-10734531-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the combination of limitations including “channel material with a band gap modulable by electric field being located adjacent to at least one layer of a negative capacitance material”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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