DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “…the passivation layer comprises a recess in an area in contact with the plurality of conductive connection members”, “wherein the plurality of conductive connection members and the assembly wiring are disposed in the recess of the passivation layer”, “the plurality of pixel electrodes are configured to form gate electrodes of the plurality of driving transistors and storage capacitors” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claims 18,20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, fails to adequately describe the plurality of pixel electrodes are configured to form gate electrodes of the plurality of driving transistors and storage capacitors, in paragraph [0033], it is recited the limitation but it is not explained how “the plurality of pixel electrodes are configured to form gate electrodes of the plurality of driving transistors and storage capacitors” and creates a lack a written description issue. In addition, this limitation is not showed in the Drawings. Due to these reasons, the limitation “the plurality of pixel electrodes are configured to form gate electrodes of the plurality of driving transistors and storage capacitors” of claim 18 has not been examined.
The specification as filed, fails to adequately describe the plurality of conductive connection members and the assembly wiring are disposed in the recess of the passivation layer, in paragraph [0033], it is recited the limitation but it is not explained how “the plurality of conductive connection members and the assembly wiring are disposed in the recess of the passivation layer” and creates a lack a written description issue. In addition, this limitation is not showed in the Drawings. Due to these reasons, claim 20 has not been examined.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, it recites the limitation “the passivation layer comprises a recess in an area in contact with the plurality of conductive connection members”. It is not clear how the passivation layer is in “contact” to the plurality of conductive connection members by a recess. According to Figure 3, the passivation layer 116 has a recess in direct contact with a first assembly wiring and in electrical contact with the plurality of conductive connection members. Therefore, it is indefinite. For the examination purpose, the limitation “the passivation layer comprises a recess in an area in contact with the plurality of conductive connection members” is interpreted as “the passivation layer comprises a recess in an area in electrical contact with the plurality of conductive connection members”.
Regarding claims 20, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4, 11, 13-15 and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (US 20210335765 A1, hereinafter Lee).
Re: Independent Claim 1, Lee teaches a display device including a semiconductor light emitting device comprising:
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Lee’s Figure 3-Annotated.
a substrate (11 in [0077], Fig. 3);
a plurality of assembly wirings (21-22 electrodes, first conductive pattern CDP, VL1 first and second voltage line VL2 in [0075,0094], Fig. 3-Annotated) disposed on the substrate (11) and comprising a first assembly wiring (21 and CDP-VL1) and a second assembly wiring (22 and VL2) arranged alternately (Figs. 2, 3-Annotated);
a planarization layer (45 a second bank in [0098], Fig. 3) having a plurality of openings (Fig. 3) overlapping the plurality of assembly wirings (overlap portions of 21 and 22);
a plurality of light emitting devices (30A as light-emitting elements 30 in [0099], Fig. 3) disposed in each of the plurality of openings (opening of 45 Fig. 3); and
a plurality of conductive connection members (26-27 contact electrodes in [0098], Fig. 3) disposed in each of the plurality of openings (opening of 45 Fig. 3) and electrically connecting the plurality of assembly wirings (21-22, VL2, CDP-VL1, Fig. 3) and the plurality of light emitting devices (30A),
wherein the planarization layer (45) is configured to protrude inside the plurality of openings (opening of 45 Fig. 3) beyond one end of the plurality of assembly wirings (one end of a portion 21P of 21 or one end of a portion 22P of 22, Fig. 3-Annotated), and
wherein one end of the plurality of assembly wiring (21-22, VL2, CDP-VL1, Fig. 3) is exposed from the planarization layer (45) and is in contact (the top portion of 21 or 22 as an end exposed by the planarization layer) with the plurality of conductive connection members (26-27).
Re: Claim 2, Lee discloses the display device including the semiconductor light emitting device according to claim 1, wherein the first assembly wiring (21 and CDP-VL1) comprises a first conductive layer (CDP-VL1) disposed on the substrate (11) and a second conductive layer (21) disposed on the first conductive layer (CDP-VL1), wherein the second assembly wiring (22 and VL2) comprises a third conductive layer (VL2) disposed on the substrate (11) and a fourth conductive layer (22) disposed on the third conductive layer (VL2), wherein the first conductive layer (CDP-VL1) and the third conductive layer (VL2) overlap the plurality of openings (Fig. 3), and wherein the second conductive layer (a portion 21P of 21, Fig. 3-Annotated) and the fourth conductive layer (a portion 22P of 22, Fig. 3-Annotated) are spaced apart from the openings (Fig. 3-Annotated).
Re: Claim 3, Lee discloses the display device including the semiconductor light emitting device according to claim 2, further comprising a passivation layer (19 first planarization layer made of an inorganic insulating in [0097], Fig. 3) disposed between the first conductive layer (CDP-VL1) and the third conductive layer (VL2) and the plurality of the light emitting devices (30A), wherein the second conductive layer (21) is electrically connected to the first conductive layer (CDP-VL1) through a contact hole (CT1 first contact hole in [0105], Fig. 3) in the passivation layer (19), and wherein the fourth conductive layer (22) is electrically connected to the third conductive layer (VL2) through a contact hole (CT2 second contact hole in [0105], Fig. 3) in the passivation layer (19).
Re: Claim 4, Lee discloses the display device including the semiconductor light emitting device according to claim 3, wherein a sidewall of the planarization (45) is disposed closer to the plurality of light emitting devices (30A) than the second conductive layer and the fourth conductive layer (a portion 21P of 21 or a portion 22P of 22, Fig. 3-Annotated) in the plurality of openings (Fig. 3).
Re: Independent Claim 11, Lee teaches a display device including a semiconductor light emitting device comprising:
a substrate (11 in [0077], Fig. 3);
a plurality of first conductive layers (first conductive pattern CDP, VL1 in [0075,0094], Fig. 3) and a plurality of third conductive layers (second voltage line VL2 in [0075,0094], Fig. 3) arranged alternately on the substrate (11) and spaced apart from each other (Fig. 3);
a passivation layer (19 first planarization layer made of an inorganic insulating in [0097], Fig. 3) disposed on the plurality of first conductive layers (CDP, VL1) and the plurality of third conductive layers (VL2);
a plurality of second conductive layers (21 electrodes in [0075,0094], Fig. 3) disposed on the passivation layer (19) and electrically connected to each of the plurality of first conductive layers (CDP, VL1);
a plurality of fourth conductive layers (22 electrodes in [0075,0094], Fig. 3) disposed on the passivation layer (19) and electrically connected to each of the plurality of third conductive layers (VL2);
a planarization layer (45 a second bank in [0098], Fig. 3) disposed on the plurality of second conductive layers (21P a portion of 21 Fig. 3-Annotated) and the plurality of fourth conductive layers (22P a portion of 22 Fig. 3-Annotated) and having a plurality of openings (Fig. 3) overlapping with the plurality of first conductive layers (CDP, VL1) and the plurality of third conductive layers (VL2);
a plurality of light emitting devices (30A as light-emitting elements 30 in [0099], Fig. 3) disposed in each of the plurality of openings, each comprising a first semiconductor layer (31 first semiconductor layer in [0157], Fig. 9) and a second semiconductor layer (32 second semiconductor layer in [0158], Fig. 9) disposed on the first semiconductor layer (31); and
a plurality of conductive connection members (26-27 contact electrodes in [0098], Fig. 3) surrounding (Fig. 3) the first semiconductor layer (31) in the plurality of openings, and
wherein one end of the plurality of second conductive layers (the top portion of 21 as an end exposed by the planarization layer, Fig. 3) is exposed from the planarization layer (45) and is in contact with the plurality of conductive connection members (26-27).
Re: Claim 13, Lee discloses the display device including the semiconductor light emitting device according to claim 11, wherein the planarization layer comprises: a first planarization layer (40 first bank Fig. 3) disposed between the plurality of second conductive layers (a central portion of 21, Fig. 3) and the passivation layer (19) and between the plurality of fourth conductive layers (a central portion of 22, Fig. 3) and the passivation layer (19) and a second planarization layer (45) disposed on the plurality of second conductive layers (portion of 21, Fig. 3) and the plurality of fourth conductive layers (portion of 22, Fig. 3) and comprising the plurality of openings (openings of 45), wherein a portion of the plurality of second conductive layers (portion of 21, Fig. 3) and a portion of the plurality of fourth conductive layers (portion of 22, Fig. 3) are disposed between the passivation layer (19) and the second planarization layer (45), wherein a remaining portion of the plurality of second conductive layers (a central portion of 21, Fig. 3) and a remaining portion of the plurality of fourth conductive layers (a central portion of 22, Fig. 3) are disposed between the first planarization layer (45) and the second planarization layer (40).
Re: Claim 14, Lee discloses the display device including the semiconductor light emitting device according to claim 11, wherein one end of the plurality of fourth conductive layers (22) is exposed from the planarization layer (45) and is configured to contact (the top portion of 22 as an end exposed by the planarization layer) with the plurality of conductive connection members (26-27).
Re: Claim 15, Lee discloses the display device including the semiconductor light emitting device according to claim 11, wherein one end (an end portion 22P of 22, Fig. 3-Annotated) of the plurality of fourth conductive layers (22) is covered by the planarization layer (45) and is spaced apart (Fig. 3-Annotated) from the plurality of conductive connection members (26-27).
Re: Claim 19, Lee discloses the display device including the semiconductor light emitting device according to claim 1, wherein the passivation layer (19) comprises a recess (CT1 or CT2) in an area in electrical contact (26-27 are electrically connected with 21 or 22 Fig. 3) with the plurality of conductive connection members (26-27).
Claims 1-4 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Lee-Sang et al. (US 20230352644 A1, hereinafter Lee-Sang).
Re: Independent Claim 1, Lee-Sang teaches a display device including a semiconductor light emitting device comprising:
a substrate (SUB in [0088], Fig. 16);
a plurality of assembly wirings (bridge pattern BRP, TE1-TE2 transistor electrodes, UE upper electrode, first electrode ELT1, second electrode ELT2 and second power line PL2, in [0094,0170,0178], Fig. 16) disposed on the substrate (SUB) and comprising a first assembly wiring (TE1-TE2, BRP, and ELT1) and a second assembly wiring (UE, PL2 and ELT2) arranged alternately (Fig. 16);
a planarization layer (BNK2 a second bank in [0154], Fig. 16) having a plurality of openings (Fig. 16) overlapping the plurality of assembly wirings (overlap portions of ELT1 and ELT2);
a plurality of light emitting devices (LD light-emitting elements in [0046], Fig. 16) disposed in each of the plurality of openings (opening of BNK2 Fig. 16); and
a plurality of conductive connection members (first contact electrode CNE1 and a second contact electrode CNE2 in [0133], Fig. 16) disposed in each of the plurality of openings (opening of BNK2 Fig. 16) and electrically connecting the plurality of assembly wirings (TE1-TE2, BRP, UE, ELT1, PL2, and ELT2, Fig. 16) and the plurality of light emitting devices (LD),
wherein the planarization layer (BNK2) is configured to protrude inside the plurality of openings (opening of BNK2 Fig. 16) beyond one end of the plurality of assembly wirings (one end of BRP or one end of PL2, Fig. 16), and
wherein one end of the plurality of assembly wiring (BRP, TE1-TE2, UE and ELT1, PL2 and ELT2, Fig. 16) is exposed from the planarization layer (BNK2) and is in contact (the top portion of ELT1 or ELT2 as one end exposed by the planarization layer) with the plurality of conductive connection members (CNE1- CNE2).
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Lee-Sang’s Figure 16-Annotated.
Re: Claim 2, Lee-Sang discloses the display device including the semiconductor light emitting device according to claim 1, wherein the first assembly wiring (TE1-TE2, BRP, and ELT1) comprises a first conductive layer (TE1-TE2, BRP) disposed on the substrate (SUB) and a second conductive layer (ELT1) disposed on the first conductive layer (TE1-TE2, BRP), wherein the second assembly wiring (UE,PL2 and ELT2) comprises a third conductive layer (PL2-UE) disposed on the substrate (SUB) and a fourth conductive layer (ELT2) disposed on the third conductive layer (PL2-UE), wherein the first conductive layer (TE1-TE2, BRP) and the third conductive layer (PL2-UE) overlap the plurality of openings (Fig. 16), and wherein the second conductive layer (ELT1, Fig. 16) and the fourth conductive layer (ELT2, Fig. 16) are spaced apart from the openings (Fig. 16).
Re: Claim 3, Lee-Sang discloses the display device including the semiconductor light emitting device according to claim 2, further comprising a passivation layer (PSV a passivation layer in [0178], Fig. 16) disposed between the first conductive layer (TE1-TE2, BRP) and the third conductive layer (PL2-UE) and the plurality of the light emitting devices (LD), wherein the second conductive layer (ELT1) is electrically connected to the first conductive layer (TE1-TE2, BRP) through a contact hole (CH1 first contact hole in [0132], Fig. 16) in the passivation layer (PSV), and wherein the fourth conductive layer (ELT2) is electrically connected to the third conductive layer (PL2-UE) through a contact hole (CH2 second contact hole in [0132], Fig. 16) in the passivation layer (PSV).
Re: Claim 4, Lee-Sang discloses the display device including the semiconductor light emitting device according to claim 3, wherein a sidewall of the planarization (BNK2) is disposed closer to the plurality of light emitting devices (LD) than the second conductive layer and the fourth conductive layer (an end portion of ELT1 and an end portion of ELT2, Fig. 16) in the plurality of openings (Fig. 16).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee-Sang (US 20230352644 A1) in view of Choi (US 20180351126 A1, hereinafter Choi).
Re: Claim 5, Lee-Sang discloses the display device including the semiconductor light emitting device according to claim 4, one end (top end of ELT1) of the second conductive layer (ELT1, Fig. 16) is exposed from the planarization layer (BNK2), and wherein the plurality of conductive connection members (CNE1- CNE2) are configured to fill insides of the plurality of openings (opening of BNK2 Fig. 16) and are contact (Fig. 16) with lower sides of the plurality of light emitting devices (LD) and one end of the second conductive layer (top end of ELT1).
Lee-Sang does not expressly disclose wherein the planarization layer and the second conductive layer are configured to form an undercut structure.
However, in the same semiconductor device field of endeavor, Choi discloses a planarization layer (isolation layer 120 positioned in the display area AA has the opening OPN defining the emission area of the sub-pixel in [0053], Fig. 4) and the second conductive layer (lower electrode layer 121 in [0054], Fig. 4) are configured to form an undercut structure (undercut formed between 120 and 121, [0092], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature of the planarization layer and the second conductive layer are configured to form an undercut structure to Lee-Sang to simplify a light-emitting display manufacturing process and to improve product competitiveness ([0006], Choi).
Re: Claim 6, Lee-Sang modified by Choi discloses the display device including a semiconductor light emitting device according to claim 5, one end (top end of ELT2) of the fourth conductive layer (ELT2, Fig. 16) is exposed from the planarization layer (BNK2), and wherein the plurality of conductive connection members (CNE1- CNE2) are configured to fill insides of the plurality of openings (opening of BNK2 Fig. 16) and are configured to contact one end (top end of ELT2) of the fourth conductive layer (ELT2, Fig. 16).
Lee-Sang modified by Choi does not expressly disclose wherein the planarization layer and the fourth conductive layer are configured to form an undercut structure.
However, in the same semiconductor device field of endeavor, Choi a planarization layer (isolation layer 120 positioned in the display area AA has the opening OPN defining the emission area of the sub-pixel in [0053], Fig. 4) and the fourth conductive layer (lower electrode layer 121 in [0054], Fig. 4) are configured to form an undercut structure (undercut formed between 120 and 121, [0092], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature of wherein the planarization layer and the fourth conductive layer are configured to form an undercut structure to Lee-Sang to simplify a light-emitting display manufacturing process and to improve product competitiveness ([0006], Choi).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee-Sang (US 20230352644 A1) in view of Choi and further in view of Kang et al (US 20220238756 A1, hereinafter Kang).
Re: Claim 7, Lee-Sang modified by Choi discloses the display device including the semiconductor light emitting device according to claim 5, wherein the planarization layer (BNK2) is configured to cover one end (a right bottom side of ELT2) of the fourth conductive layer (ELT2).
Lee-Sang modified by Choi does not expressly disclose wherein the plurality of conductive connection members are separated from the fourth conductive layer by the planarization layer.
However, in the same semiconductor device field of endeavor, Kang discloses a planarization layer (600-510 first bank 600 and second insulating layer 510 in [0084, 0098], Fig. 3) wherein the plurality of conductive connection members (710-720 first and second contact electrodes 710 and 720 in ([0098], Fig. 3) are separated (Fig. 3) from the fourth conductive layer (220 electrodes in ([0098], Fig. 3) by the planarization layer (600-510).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kang’s feature of wherein the plurality of conductive connection members are separated from the fourth conductive layer by the planarization layer to the combination of Lee-Sang and Choi to simplify a light-emitting display manufacturing process and for having an improved emission efficiency ([0007], Kang).
Claim(s) 8-10 and 16-18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee in view of Park et al (US 20200212102 A1, hereinafter Park).
Re: Claim 8, Lee discloses the display device including the semiconductor light emitting device according to claim 1.
Lee does not expressly disclose a plurality of pixel electrodes disposed on the planarization layer and electrically connected to the plurality of light emitting devices and; a plurality of insulating members disposed between the plurality of conductive connection members and the plurality of pixel electrodes in each of the plurality of openings.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4) disposed on the planarization layer (160 planarization layer in [0080], Fig. 4) and electrically connected to the plurality of light emitting devices (150 a light emitting diode in [0080], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of pixel electrodes disposed on the planarization layer and electrically connected to the plurality of light emitting devices to Lee to obtain a plurality of insulating members disposed between the plurality of conductive connection members and the plurality of pixel electrodes in each of the plurality of openings to high efficiency, thinned, and weight-lightened ([0006], Park).
Re: Claim 9, Lee modified by Park discloses the display device including the semiconductor light emitting device according to claim 8.
Lee modified by Park does not expressly disclose further comprising a plurality of driving transistors disposed between the substrate and the plurality of assembly wirings, and wherein the plurality of pixel electrodes electrically are configured to connect the plurality of driving transistors and the plurality of light emitting devices through contact holes in the planarization layer.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of driving transistors (T2 driving TFT in [0058], Fig. 4) disposed between the substrate (100 display substrate in [0046], Fig. 4) and the plurality of assembly wirings (E1- E2 electrodes in [0093], Fig. 4), and wherein the plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4) electrically are configured to connect the plurality of driving transistors (T2) and the plurality of light emitting devices (150 a light emitting diode in [0080], Fig. 4) through contact holes (contact holes in layer 160, Fig. 4) in the planarization layer (160 planarization layer in [0080], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of driving transistors disposed between the substrate and the plurality of assembly wirings, and wherein the plurality of pixel electrodes electrically are configured to connect the plurality of driving transistors and the plurality of light emitting devices through contact holes in the planarization layer to the combination of Lee and Park to high efficiency, thinned, and weight-lightened ([0006], Park).
Re: Claim 10, Lee modified by Park discloses the display device including the semiconductor light emitting device according to claim 8.
Lee modified by Park does not expressly disclose further comprising a plurality of driving transistors disposed on the plurality of pixel electrodes, and wherein the plurality of pixel electrodes are reflective electrodes.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of driving transistors (T2 driving TFT in [0058], Fig. 4) disposed on the plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4), and wherein the plurality of pixel electrodes (PE) are reflective electrodes ([0098]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of driving transistors disposed on the plurality of pixel electrodes, and wherein the plurality of pixel electrodes are reflective electrodes to the combination of Lee and Park to high efficiency, thinned, and weight-lightened ([0006], Park).
Re: Claim 16, Lee discloses the display device including the semiconductor light emitting device according to claim 11.
Lee does not expressly disclose a plurality of pixel electrodes disposed on the planarization layer and electrically connected to the second semiconductor layer of each of the plurality of light emitting devices and a plurality of insulating members surrounding the plurality of light emitting devices between the plurality of pixel electrodes and the plurality of conductive connection members.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4) disposed on the planarization layer (160 planarization layer in [0080], Fig. 4) and electrically connected the second semiconductor layer (157 second semiconductor layer in [0103], Fig. 4) of each of the plurality of light emitting devices (150 a light emitting diode in [0080], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of pixel electrodes disposed on the planarization layer and electrically connected to the second semiconductor layer of each of the plurality of light emitting devices to Lee to obtain a plurality of insulating members disposed between the plurality of conductive connection members and the plurality of pixel electrodes in each of the plurality of openings to high efficiency, thinned, and weight-lightened ([0006], Park).
Re: Claim 17, Lee modified by Park discloses the display device including the semiconductor light emitting device according to claim 16.
Lee modified by Park does not expressly disclose further comprising a plurality of driving transistors disposed between the passivation layer and the substrate and electrically connected to the plurality of pixel electrodes.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of driving transistors (T2 driving TFT in [0058], Fig. 4) disposed between the passivation layer (110 passivation layer in [0080], Fig. 4) and the substrate (100 display substrate in [0046], Fig. 4) and electrically connected (Fig. 4) to the plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of driving transistors disposed between the passivation layer and the substrate and electrically connected to the plurality of pixel electrodes to the combination of Lee and Park to high efficiency, thinned, and weight-lightened ([0006], Park).
Re: Claim 18, Lee modified by Park discloses the display device including the semiconductor light emitting device according to claim 16.
Lee modified by Park does not expressly disclose further comprising a plurality of driving transistors disposed on the plurality of pixel electrodes.
However, in the same semiconductor device field of endeavor, Park discloses a plurality of driving transistors (T2 driving TFT in [0058], Fig. 4) disposed on the plurality of pixel electrodes (PE pixel electrode in [0080], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Park’s feature of a plurality of driving transistors disposed on the plurality of pixel electrodes to the combination of Lee and Park to high efficiency, thinned, and weight-lightened ([0006], Park).
Claim(s) 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee in view of Choi (US 20180351126 A1, hereinafter Choi).
Re: Claim 12, Lee discloses the display device including the semiconductor light emitting device according to claim 11, wherein the planarization layer (45) is configured to protrude inside the plurality of openings (opening of 45 Fig. 3) beyond one end of the plurality of second conductive layers (one end of a portion 21P of 21, Fig. 3-Annotated).
Lee does not expressly disclose wherein the planarization layer and the plurality of second conductive layers are configured to form an undercut structure.
However, in the same semiconductor device field of endeavor, Choi discloses a planarization layer (isolation layer 120 positioned in the display area AA has the opening OPN defining the emission area of the sub-pixel in [0053], Fig. 4) and the plurality of second conductive layers (lower electrode layer 121 in [0054], Fig. 4) are configured to form an undercut structure (undercut formed between 120 and 121, [0092], Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature wherein the planarization layer and the plurality of second conductive layers are configured to form an undercut structure to Lee to obtain which one end of the plurality of second conductive layers is exposed from the planarization layer to simplify a light-emitting display manufacturing process and to improve product competitiveness ([0006], Choi).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tae et al (US 20240055566 A1) teaches “DISPLAY DEVICE”. This document is related to a display device in accordance with one or more embodiments may include: a substrate including a display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and a non-display area at least one side of the display area; and a pixel in each of the plurality of pixel areas. The pixel may include: a first electrode and a second electrode spaced from each other on the substrate; a plurality of light emitting elements connected between the first and the second electrodes; and an optical pattern on the plurality of light emitting elements and overlapping at least some of the plurality of light emitting elements. The optical pattern is configured to extract light emitted from the plurality of light emitting elements.
Cho et al. (US 20230369542 A1) teaches “LIGHT-EMITTING DEVICE, MANUFACTURING METHOD FOR LIGHT-EMITTING DEVICE, AND DISPLAY APPARATUS”. This document is related to a light-emitting device includes a light-emitting device core including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an element active layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating layer disposed on the side surface of the light-emitting device core to surround the side surface of the light-emitting device core, and having first fixed charges; and a second insulating layer surrounding the outer side surface of the first insulating layer, and including a material having second fixed charges different from the first fixed charges.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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