DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gardner et al. (U.S. Patent No. 6,005,285; hereinafter Gardner)
With respect to claim 1, Gardner discloses a field effect transistor device with a blocking region, comprising an active layer [20], wherein the active layer comprises a source region [36a], a drain region [36b] and a channel region located between the source region and the drain region, wherein the channel region is provided with a carrier blocking region [26]; wherein the carrier blocking region serves to block carriers moving from the source region to the drain region when the device is turned off (See Column 8, lines 21-57).
With respect to claim 2, Gardner discloses wherein the carrier blocking region is an insulating region or a semi-insulating region (see Figure 4 and Column 6, lines 43-51)
With respect to claim 3, Gardner discloses wherein an interface of the carrier blocking region and the channel region forms a barrier for preventing carriers from entering the carrier blocking region (See Column 8, lines 21-57).
With respect to claim 4, Gardner discloses wherein a dielectric constant of the carrier blocking region is less than a dielectric constant of the channel region (see Figure 4 and Column 6, lines 43-51 and Column 8, lines 21-57).
With respect to claim 5, Gardner discloses wherein the carrier blocking region is a dielectric material filled in a trench of the channel region (see Figure 4 and Column 6, lines 43-51).
With respect to claim 6, Gardner discloses wherein the carrier blocking region is an insulating region or a semi-insulating region formed by ion implantation or doping in the channel region (see Figure 4 and Column 6, lines 43-51 and Column 8, lines 21-57).
With respect to claim 7, Gardner discloses wherein the carrier blocking region is a dielectric material formed on a substrate [10], and the active layer is prepared on the substrate on which the dielectric material is formed (see Figure 4 and Column 6, lines 43-51 and Column 8, lines 21-57).
With respect to claim 13, Gardner fails to explicitly disclose wherein the ratio of the length of the carrier blocking region to the length of the channel region ranges from 0.5 to 0.7 (See Figure 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Park (U.S. Publication No. 2004/0065936 A1)
With respect to claim 8, Gardner fails to disclose wherein the carrier blocking region is selected from a dielectric material of any one or a combination of gallium arsenide single crystal, silicon dioxide, silicon nitride, zirconium dioxide, aluminum oxide, hafnium oxide, tantalum oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium silicate, zirconium aluminate, silicon oxynitride, titanium oxide, hafnium dioxide-aluminum oxide alloy having a room temperature resistivity greater than 1×105 Ω·cm.
In the same field of endeavor, Park teaches wherein the carrier blocking region [340] is selected from a dielectric material of any one or a combination of gallium arsenide single crystal, silicon dioxide, silicon nitride, zirconium dioxide, aluminum oxide, hafnium oxide, tantalum oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium silicate, zirconium aluminate, silicon oxynitride, titanium oxide, hafnium dioxide-aluminum oxide alloy having a room temperature resistivity greater than 1×105 Ω·cm (see ¶[0028]). Implementation of a dielectric carrier blocking region as taught by Park allows for the prevention of additional depletion regions (See Park ¶[0028]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Kimizuka et al. (U.S. Patent No. 7,102,183 B2; hereinafter Kimizuka)
With respect to claim 9, Gardner teaches wherein the field effect transistor further comprises a channel formed in the channel region when turned on, the carrier blocking region having a spacing from the channel in a thickness direction of the active layer (see Figure 6); but fails to disclose the width of the carrier blocking region is equal to the width of the channel region.
In the same field of endeavor, Kimizuka teaches the carrier blocking region having a spacing from the channel [105] in a thickness direction of the active layer; the width of the carrier blocking region [150] is equal to the width of the channel region (see Figure 3C). Implementation of a full width of the carrier blocking region as taught by Kimizuka allows for inhibition of short-channel effect (see Column 3, lines 65 to Column 4, line 2). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Sohn (U.S. Publication No. 2004/0053457 A1)
With respect to claim 12, Gardner fails to disclose wherein the carrier blocking region is fluorine ion implanted silicon or iron ion implanted gallium arsenide.
In the same field of endeavor, Sohn teaches wherein the carrier blocking region [71] is fluorine ion implanted silicon (see ¶[0050] and ¶[0109]). Implementation of fluorine ion implantation as taught by Sohn improves punch-through characteristics and prevention of junction resistance increase (See ¶[0116]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 10, none of the prior art teaches or suggests, alone or in combination, wherein the carrier blocking region comprises a first carrier blocking region and a second carrier blocking region, and orthographic projections of the first carrier blocking region and the second carrier blocking region on a plane perpendicular to the channel direction at least partially overlap.
With respect to claim 11, none of the prior art teaches or suggests, alone or in combination, wherein the carrier blocking region is an air atmosphere, an inert gas atmosphere or a vacuum.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Hoffman et al. (U.S. Publication No. 2014/0084385 A1) discloses a transistor with carrier blocking but fails to disclose wherein the carrier blocking region comprises a first carrier blocking region and a second carrier blocking region, and orthographic projections of the first carrier blocking region and the second carrier blocking region on a plane perpendicular to the channel direction at least partially overlap or wherein the carrier blocking region is an air atmosphere, an inert gas atmosphere or a vacuum.
- - Riccobene et al. (U.S. Patent No. 6,538,284 B1) discloses a transistor with carrier blocking but fails to disclose wherein the carrier blocking region comprises a first carrier blocking region and a second carrier blocking region, and orthographic projections of the first carrier blocking region and the second carrier blocking region on a plane perpendicular to the channel direction at least partially overlap or wherein the carrier blocking region is an air atmosphere, an inert gas atmosphere or a vacuum.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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