Prosecution Insights
Last updated: October 02, 2026
Application No. 18/709,937

SEMICONDUCTOR DEVICE AND PHOTODETECTOR

Non-Final OA §102§103
Filed
May 14, 2024
Priority
Nov 22, 2021 — JP 2021-189619 +1 more
Examiner
SYLVIA, CHRISTINA A
Art Unit
Tech Center
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
675 granted / 771 resolved
+27.5% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
25 currently pending
Career history
795
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
59.1%
+19.1% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 771 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 05/14/2024. Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-7 and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (PG Pub 2013/0093009; hereinafter Chen). PNG media_image1.png 536 948 media_image1.png Greyscale Regarding claim 1, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches a semiconductor device 200 comprising: a PN junction diode (see claim limitations below) including an N-type first semiconductor region 28 and a P-type second semiconductor region 26 that ae disposed in contact with each other at a PN junction surface (annotated “pn” in Fig. 3); a third semiconductor region 202 that is separated from the first semiconductor region and the second semiconductor region and is provided for discharge in a depletion layer formed around the PN junction surface when a reverse bias voltage is applied to the PN junction diode; a first electrode (“elec-1”) connected to the first semiconductor region (see Fig. 3); a second electrode (“elec-2”) connected to the second semiconductor region (see Fig. 3); and a third electrode 210 connected to the third semiconductor region (see Fig. 3). The recited “is provided for discharge in a depletion layer formed around the PN junction surface when a reverse bias voltage is applied to the PN junction diode)” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the function is having the same claimed pn-diode structure, which Chen clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on."). Regarding claim 2, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the third semiconductor region 202 is disposed as high as the first semiconductor region 28 and the second semiconductor region 26 (all regions have their top surface on the same plane) and is disposed closer to the second semiconductor region than the first semiconductor region (see Fig. 3). Regarding claim 3, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the third semiconductor region 202 is disposed as high as the first semiconductor region 28 and the second semiconductor region 26 (see Fig. 3) and is disposed to surround (on the left side) the first semiconductor region and the second semiconductor region (see Fig. 3). Regarding claim 4, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the first semiconductor region 28 and the second semiconductor region 26 are disposed near a first principal surface (“principal-1”) of a semiconductor substrate 20, and the third semiconductor region 202 is disposed near a second principal surface (“principal-2”) opposite to the first principal surface of the semiconductor substrate (see Fig. 3). Regarding claim 5, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the first semiconductor region 28 and the second semiconductor region 26 are disposed near a first principal surface (“principal-1”) of a semiconductor substrate 20, and the third semiconductor region 202 is disposed near a second principal surface (“principal-2”) opposite to the first principal surface of the semiconductor substrate (see Fig. 3) and is disposed to surround the first semiconductor region and the second semiconductor region from a side (the left side thereof) of the second principal surface to a side of the first principal surface (see Fig. 3). Regarding claim 6, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the first semiconductor region 28, the second semiconductor region 26, and the third semiconductor region 202 are disposed at the same layer height (vertical distance from substrate bottom to substrate top), the second semiconductor region 26 is disposed to surround the first semiconductor region 28 9from the left side), and the third semiconductor region 202 is disposed to surround the second semiconductor region 26 (from the right side) (see Fig. 3). Regarding claim 7, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches a well region 21 in which the first semiconductor region 28, the second semiconductor region 26, and the third semiconductor region 202 are disposed (see Fig. 3), and an element isolation region 208 disposed to surround the well region (on at least the left side). Regarding claim 10, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the element isolation region 208 is disposed to penetrate a semiconductor substrate 20 where the well region 205 is disposed (see Fig. 3). Regarding claim 11, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the third semiconductor region 202 is N-type (see Fig. 3), and the third electrode 210 discharges electrons in the depletion layer through the third semiconductor region when the reverse bias voltage is applied to the PN junction diode (“pn”). The recited “discharges electrons in the depletion layer through the third semiconductor region when the reverse bias voltage is applied to the PN junction diode” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having the structure as outlined in claim 1 with the doping profile of claim 11; which Chen clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on."). Regarding claim 12 and claim 13, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches: (Regarding claim 12) the first electrode (elec-1) is a cathode electrode, and the third electrode 202 is set at a higher voltage than the cathode electrode when the reverse bias voltage is applied to the PN junction diode; (Regarding claim 13) wherein the third electrode is set at the same voltage as the cathode electrode when a forward bias voltage is applied to the PN junction diode, and the third electrode is set at a higher voltage than the cathode electrode when the reverse bias voltage is applied to the PN junction diode. The recited “the third electrode is set at a higher voltage than the cathode electrode when the reverse bias voltage is applied to the PN junction diode” and “the third electrode is set at the same voltage as the cathode electrode when a forward bias voltage is applied to the PN junction diode, and the third electrode is set at a higher voltage than the cathode electrode when the reverse bias voltage is applied to the PN junction diode” (i.e., manner of operating) do not structurally distinguish an apparatus claim from the prior art apparatus see MPEP 2114 (II) states "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 7 above, and further in view of Marreiro et al. (PG Pub 2017/0077082; hereinafter Marreiro). Regarding claim 8, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches claim 7, wherein the element isolation region is as deep as or deeper than the first semiconductor region and the second semiconductor region. Regarding claim 9, refer to the Examiner’s mark-up of Fig. 3 provided above, Chen teaches the element isolation region 208, Chen does not teach the element isolation region is as deep as or deeper than the well region. PNG media_image2.png 168 506 media_image2.png Greyscale In the same field of endeavor, refer to Fig. 4a-provided above, Marreiro teaches a pn-junction device comprising: an element isolation region 204; wherein the element isolation region is as deep as or deeper than a well region 203 (see Fig. 4a). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the element isolation region of Chen be as deep as or deeper than the well region, as taught by Marreiro, to define boundaries between sections of the device (para [0028]). Allowable Subject Matter 3. Claims 14-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, the third semiconductor region is P-type, and the third electrode discharges holes in the depletion layer through the third semiconductor region when the reverse bias voltage is applied to the PN junction diode. Claims 15-16 would be allowable, because they depend on allowable claim 14. Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, a light receiving element that receives an inputted optical signal; and a voltage generating unit that generates a reverse bias voltage to be applied to the light receiving element, wherein the voltage generating unit includes a charge pump that generates the reverse bias voltage with the PN junction diodes cascaded in multiple stages in the semiconductor device according to claim 1. Claims 18-20 would be allowable, because they depend on allowable claim 17. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 14, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.6%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 771 resolved cases by this examiner. Grant probability derived from career allowance rate.

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