Prosecution Insights
Last updated: October 01, 2026
Application No. 18/710,191

DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
May 15, 2024
Priority
Nov 17, 2021 — CN 202111362915.3 +1 more
Examiner
OJEH, NDUKA E
Art Unit
Tech Center
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
729 granted / 812 resolved
+29.8% vs TC avg
Minimal -2% lift
Without
With
+-2.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
20 currently pending
Career history
816
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 812 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 1/2/2025, 3/31/2025, 1/13/2026 and 3/19/2026 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification The abstract is consistent with the requirements set forth in the MPEP 608.01(b). The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DISPLAY PANEL COMPRISING ISOLATION PORTION WITH GROOVE AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 9-10, 13 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon et al. US PGPub. 2021/0217992. Regarding claim 1, Moon teaches a display panel (1, fig. 1 and 12) [0101] comprising: a hole (OA, fig. 1, 12) [0102], a transition region (MA, fig. 1 and 12) [0103] surrounding the hole (OA), and an image display region (DA, fig. 1, 12) [0102] surrounding the transition region (MA); a substrate (101, fig. 12) [0175]; a display layer (221+222+223, fig. 12; collectively called OLED) [0174] located on a(top) side of the substrate (101), wherein the hole (OA) runs through (fig. 12) the display layer (OLED), the display layer (OLED) comprises a cathode (223, fig. 12) [0174] having a first cathode portion (cathode 223 portion in the MA region XIII of fig. 12-13; hereinafter called 223-MA) located in the transition region (MA); an isolation column (103+104, fig. 12-13) [0176-0177] located on the (top) side of the substrate (101) and in the transition region (MA); and a part of a first film layer (102, fig. 12-12) [0177] located on a (bottom) side of the isolation column (103+104) facing the image display region (DA), wherein the isolation column (103+104) comprises an insulation isolation portion (103+104, fig. 12-13) [0176]-[0177], a part of a side wall (R1, fig. 13) of the insulation isolation portion (103+104) is recessed toward an inside of the insulation isolation portion (103+104) to form a groove (G, fig. 13) [0132], a first (top) surface of a side that is of the insulation isolation portion (103+104) is away from the substrate (101) and the first cathode portion (223-MA) extending on the first film layer (102) is separated at the groove (G) from the first cathode portion (223-MA) extending on the first surface (top surface of 103+104) (Moon et al., fig. 1 and 12-13). Regarding claims 9 and 21, Moon teaches the display panel and an electronic device according to claims 1 and 13, wherein the display panel (1) further comprises a dam (510, fig. 12) [0192] located in the transition region (MA), and a subset of the isolation columns (two sets of 103+104, fig. 12) are located on a (left) side of the dam (510) close to the hole (OA) (Moon et al., fig. 12). Regarding claim 10, Moon teaches a manufacturing method for manufacturing a display panel (1, fig. 1 and 12) [0101], comprising: providing a substrate (101, fig. 12) [0175], wherein the substrate (101) comprises a preset hole region (OA, fig. 1, 12) [0102], a transition region (MA, fig. 1 and 12) [0103] surrounding the preset hole region (OA), and an image display region (DA, fig. 1, 12) [0102] surrounding the transition region (MA); forming a first film layer (102, fig. 12-12) [0177] in the preset hole region (OA), the transition region (MA), and the image display region (DA) of the substrate (101); forming an isolation column (103+104, fig. 12-13) [0176-0177] on the first film layer (102), wherein the isolation column (103+104) is located in the transition region (MA) and comprises an insulation isolation portion (103+104, fig. 12-13) [0176-0177]; recessing [0184] a part of a side wall of the insulation isolation portion (103+104) toward an inside of the insulation isolation portion (103+104) to form a groove (G, fig. 13) [0132], wherein a first (top) surface of a side of the insulation isolation portion (103+104) is away from the substrate (101), and a second (bottom) surface of the insulation isolation portion (103+104) is in contact (indirect contact) with the first film layer (102); forming a display layer (221+222+223, fig. 12; collectively called OLED) [0174] in the preset hole region (OA), the transition region (MA), and the image display region (DA) of the substrate (101), wherein the display layer (OLED) comprises a cathode (223, fig. 12) [0174] having a first cathode portion (cathode 223 portion in the MA region XIII of fig. 12-13; hereinafter called 223-MA) located in the transition region (MA), and the first cathode portion (223-MA) extending on the first film layer (102) is separated at the groove (G) from the first cathode portion (223-MA) extending on the first surface (top surface of 103+104]); and cutting the substrate (101), the first film layer (102), and the display layer (DA) along an edge of the preset hole region (OA) to form a hole (OA, [0102]) (Moon et al., fig. 12). Regarding claim 13, Moon teaches an electronic device (1, fig. 1 and 12) [0104] comprising: a display panel (fig. 12), wherein the display panel comprises: a hole (OA, fig. 1, 12) [0102], a transition region (MA, fig. 1 and 12) [0103] surrounding the hole (OA), and an image display region (DA, fig. 1, 12) [0102] surrounding the transition region (MA); a substrate (101, fig. 12) [0175]; a display layer (221+222+223, fig. 12; collectively called OLED) [0174], located on a (top) side of the substrate (101), wherein the hole (OA) runs through the display layer (OLED), the display layer (OLED) comprises a cathode (223, fig. 12) [0174] having a first cathode portion (cathode 223 portion in the MA region XIII of fig. 12-13; hereinafter called 223-MA) located in the transition region (MA); an isolation column (103+104, fig. 12-13) [0176-0177] located on the side of the substrate (101) and located in the transition region (MA); and a first film layer (102, fig. 12-12) [0177] in contact with the isolation column (103+104) and located on a (bottom) side of the isolation column (103+104) facing the substrate (101), wherein the isolation column (103+104) comprises an insulation isolation portion (103+104, fig. 12-13) [0176-0177], a part of a side wall (R1, fig. 13) of the insulation isolation portion (103+104) is recessed toward an inside of the insulation isolation portion to form a groove (G, fig. 13) [0132], a first (top) surface of a side of the insulation isolation portion (103+104) is away from the substrate (101), and a second (bottom) surface of a side of the insulation isolation portion (103+104) facing the substrate (101) is in contact (indirect contact) with the first film layer (102), and the first cathode portion (223-MA) extending on the first film layer (102) is separated at the groove (G) from the first cathode portion (223-MA) extending on the first surface (top surface of 103+104) (Moon et al., fig,. 1 and 12-13). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-4 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. US PGPub. 2021/0217992 as applied to claim 1 above, and further in view of Choi US PGPub. 2024/0423016. Regarding claims 2 and 14, Moon does not teach the display panel and electronic device according to claims 1 and 13, wherein the insulation isolation portion (103+104) is of an integrated structure. Layers 103 and 104 are made of polymer resin (103, [0176]) and silicon nitride/silicon oxide (104, [0177]), respectively. However, Choi teaches a display panel (1, fig. 1 and 8) [0062] comprising an insulation isolation structure (205, fig. 8)[0110] comprising a groove (G, fig. 8)[0124], wherein the insulation isolation portion (205) is of an integrated structure (fig. 8) (Choi, fig. 8). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the insulation isolation portion of Moon made up of two different layers/materials for the insulation isolation portion of Choi made up of an integrated structure in order to save on material and ease of manufacturing by using a single process for a single material instead of multiple processes and because it has also been held that the use of one piece construction instead of the multiple structure disclosed in a prior art would be merely a matter of obvious engineering choice in the absence of insight contrary to the understanding and expectations of the art (see MPEP 2144.04.V.B) Regarding claims 3 and 15, Moon in view of Choi teaches the display panel and electronic device according to claims 2 and 14, wherein the insulation isolation portion (103+104) is an organic insulation layer (103 is polymer resin, [0176]) (Moon et al., fig. 12, [0176]). Regarding claims 4 and 16, Moon does not teach the display panel and electronic device according to claims 1 and 13, wherein the isolation column (103+104) further comprises a metal isolation portion located at the groove (G), a third surface of a side of the metal isolation portion away from the substrate (101) is furthest away from the substrate (101), and the insulation isolation portion (103+104) covers the third surface. However, Choi teaches a display panel (1, fig. 1 and 8) [0062] comprising an insulation isolation structure (205, fig. 8)[0110] comprising a groove (G, fig. 8)[0124], wherein the isolation structure (205) further comprises a metal isolation portion (400, fig. 8) [0126] located at the groove (G), a third (top) surface of a side of the metal isolation portion (400) away from the substrate (100, fig. 8) [0081] is furthest away from the substrate (100), and the insulation isolation portion (205) covers the third surface (top surface of 400) (Choi, fig. 8). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the insulation isolation portion of Moon such that it have the metal isolation portion in the manner as taught by Choi because such structure is well known in the art and such material/structure is art recognized and obvious to be present or not, during the process of forming the gate electrode (Choi, [0126]) (see MPEP 2144.07). Allowable Subject Matter Claims 5-8, 11 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a display panel and an electronic device wherein “in a direction perpendicular to a plane on which the substrate is located, the groove comprises a first side and a second side that are opposite to each other, and wherein the metal isolation portion comprises a first metal portion and a second metal portion, the first metal portion is located on the first side of the groove, the second metal portion is located on the second side of the groove, and there is a spacing between the first metal portion and the second metal portion” as recited in claims 5 and 17 in combination with the rest of the limitations of claims 1 and 4, and 13 and 16, respectively; a display panel and an electronic device wherein “the insulation isolation portion comprises two grooves that are opposite to each other, the isolation column comprises two metal isolation portions, and the two metal isolation portions are respectively located in the two grooves, and wherein the insulation isolation portion comprises a first insulation portion and a second insulation portion, the first insulation portion is located between the two metal isolation portions, the second insulation portion covers a side wall of the first insulation portion and a surface of a side of the first insulation portion and away from the substrate, and the second insulation portion further covers third surfaces of the two metal isolation portions” as recited in claims 7 and 19 in combination with the rest of the limitations of claims 1 and 4, and 13 and 16, respectively; and a manufacturing method wherein “the transition region comprises a preset groove region, and after the step of forming the first film layer, the manufacturing method further comprises: forming a sacrificial metal portion on the first film layer, wherein the sacrificial metal portion is located in the preset groove region, and wherein the steps of forming the insulation isolation portion on the first film layer and recessing the part of the side wall of the insulation isolation portion toward the inside of the insulation isolation portion to form the groove comprise: forming the insulation isolation portion on the first film layer, wherein the insulation isolation portion covers the sacrificial metal portion; and removing the sacrificial metal portion, so that a side wall of the insulation isolation portion in contact with the sacrificial metal portion forms the groove” as recited in claim 11 in combination with the rest of the limitations of claim 10. Claims 6, 8, 18 and 20 are also objected to as allowable for further limiting and depending upon allowable claims 5, 7, 17 and 19. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. US PGPub. 2021/0143237, Lee US PGPub. 2020/0303478 and Sung et al. US PGPub. 2020/0127233 all teach a display panel comprising an isolation structure in a transition area wherein the isolation structure comprises a groove or undercut/overhang structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NDUKA E OJEH/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
88%
With Interview (-2.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 812 resolved cases by this examiner. Grant probability derived from career allowance rate.

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