Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kumar et al (US2018/0374736) (herein “Kumar”).
Referring to claim 1. Kumar et al (herein “Kumar”) discloses an “Electrostatic Carrier For Die Bonding Applications”. See Figs. 1-20 and respective potions of the specification. Kumar further discloses a processing system configured to process multiple chips (dies), comprising a chip placing apparatus configured to pick up chips and dispose them on an attraction surface of a first electrostatic carrier. Kumar further discloses a chip placing apparatus configured to pick up and dispose on an attraction surface of a first electrostatic carier (loading robot 770 with gripper 778, picks up dies 780 and places them on electrostatic carrier 100) (See (¶¶0032-0034, Figs. 7-9A); wherein the chip placing apparatus comprises: a placement carrier holder configured to hold the first electrostatic carrier (carrier-holding platform 140 configured to receive and hold electrostatic carrier 100) (¶¶0027, 0033, Fig. 7); and a power supply configured to apply a volage to the first electrostatic carrier held by the placement carrier holder (power source 145 connected to pogo pins 142, 144 configured to deliver AC or DC electrical power to electrodes 120A, 120B of electrostatic carrier 100 when pogo pins contact contact pads 116, 118) (¶¶0027, 0033, Fig. 7).
Referring to claim 10. Kumar discloses the system as described above as set forth above as applied to claim 1. Kumar discloses an electrostatic carrier configured to hold and transfer multiple chips, the electrostatic carrier comprising: a main body having electrical insulation property (body 110 fabricated from one or more layers of dielectric material vertically stacked on each other with middle layer 135 made of dielectric material to avoid electrical arcing issues) (¶¶0021-0023, Fig. 1); multiple attraction electrodes disposed inside the main body, and arranged to respectively correspond to the multiple chips (bipolar electrostatic chucking electrode 120 with electrodes 120A, 120B disposed with layer 113 of body 110, likewise Kumar discloses an alternative embodiment with multiple bipolar chucking electrodes 520 each configured to electrostatically attract and secure one die 580 on top surface 512 of electrostatic carrier 500) (¶¶0024-0025, 0030, Figs. 2-5); and a control terminal disposed inside the main body, and configured to control application of a voltage to each of the multiple attraction electrodes independently (controller 615 configured to control the second bipolar chucking electrode 120 independently relative to the first bipolar chucking electrode 120 independently controlling the states of switches 125, 125’, contact pads 116, 118 serve as control terminals electrically connected to electrodes 120A, 120B)(¶0031, Fig. 6); wherein the multiple chips are attracted to and held on an attraction surface of the electrostatic carrier by an electrostatic force generated by application of the voltage to each of the multiple attraction electrodes independently (Kumar discloses the positive and negative charge applied on the electrodes 120A, 120B generate an electrostatic force on the top surface 112 that attracts and secures a plurality of dies to the electrostatic carrier) (¶0027).
(100) a body (110) having a top surface (112) serving as the attraction surface upon which a plurality of dies (78) are attracted and held (See Sect. 0021), a main body having an electrical insulation property, and that the body (110) of the electrostatic carrier (100) is fabricated from one or more layers of dielectric material vertically stacked on each other, including a middle layer (115) made of dielectric material to avoid electrical arcing issues and additional layers (113, 117) made of dielectric material such as ceramic or polyimide material (Sect. 0022-0024). Further, Kumar discloses multiple attraction electrodes disposed inside the main body and specifically that an electrostatic carrier (500) having a plurality of interdigitated bipolar chucking electrodes (520) disposed within the body, wherein each bipolar chucking electrode (520) is configured to electrostatically attract and secure one die (580) on the top surface (512) of the electrostatic carrier, such that multiple attraction electrodes correspond respectively to the multiple chips (Sect. 0030). Moreover, Kumar discloses a control terminal disposed inside the main body configured to control application of voltage to each of the multiple attraction electrodes independently and that controller (615) controls the open and closed states of switches (125, 125’) to independently control the voltage applied to a first bipolar chucking electrode (120) and a second bipolar chucking electrode (120’) independently of one another, wherein the controller may be located inside the electrostatic carrier (Sect. 0031).
Claim(s) 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al (US2018/0374736) in view of Hsiao (US20120227886).
Referring to claim 2. Kumar discloses the system as described above as set forth above as applied to claim 1. Kumar further discloses that the chip placing apparatus comprise means for independently controlling the holding state of each chip on the electrostatic carrier. Specifically, Kumar discloses a controller (615) that controls the open and closed states of switches (125, 125’) to independently control a first bipolar chucking electrode (120) relative to a second bipolar chucking electrode (120’), wherein each bipolar chucking electrode is configured to electrostatically attract and secure one die, thereby enabling the holding state of each die to be controlled independently (See Sect. 0030-0031). Kumar does not disclose a communicator configured to transmit a holding control signal for controlling a holding state of each of the multiple chips independently to the first electrostatic carrier. Hsiao discloses a “Substrate Assembly Carrier Using Electrostatic Force”. See Figs. 1-20 and respective portions of the specification. Hsiao further discloses a fully sealed electrostatic chuck carrier having signal receptors (80, 82), disposed within the electrostatic chuck carrier, wherein signal receptor (80) receives an optical activation signal transmitted from outside the carrier, which signal is used to activate charge station (72) to charge the electrodes (28), while signal receptor (82) receives a separate signal, which is transferred to activate discharge station (74) to discharge the electrodes. Thus, Hsiao teaches a communicator configured to receive transmitted holding control signals that control the charge state and holding state of the electrodes within the electrostatic carrier (Sect. 0024). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kumar to incorporate the wireless signal receptor of Hsiao for transmitting holding control signals to the electrostatic carrier in order to enable remote, contactless control of the electrode activation state while the carrier is in operation.
Claim(s) 3-4, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al (US2018/0374736) in view of Kiyota (WO2018135492).
Referring to claim 3. Kumar discloses the system as described above as applied to claims 1-2. Kumar discloses the electrostatic carrier (100) holds a plurality of dies (780) on its top surface (attraction surface, 112) via an electrostatic force generated by bipolar chucking electrodes, and transports the dies through subsequent processing and assembly operations (See Sect. 006, 0020, 0034, 0040). Kumar does not disclose a protective film forming apparatus, a processing apparatus configured to grind a non-holding surface side of each of the multiple chips that is not held by the first electrostatic carrier or a protective film removing apparatus configured to remove the first protective film remaining on the attraction side of the first electrostatic carrier. Kiyota discloses a “Method of Processing Semiconductor substrate and device for processing semiconductor substate”. See Figs. 1-30 and respective portions of the specification. Kiyota further discloses a protective film forming apparatus via applying a hardening agent for a protective film to the one surface side of a semiconductor substate on which a plurality of integrated circuit chips are formed, supplying energy to the hardening agent to cure it, and thereby forming a protective film layer on the chip-bearing surface side of the substrate (See Sect. 0009, 0012), a processing apparatus configured to grind the non-holding surface, by teaching shaving (grinding and polishing) the other surface side, the back surface of the semiconductor substate to reduce its thickness after the protective film has been formed on the chip-bearing front surface side (See Sect. 0009, 0013), and a protective film removing apparatus through teaching irradiating the protective film with laser light to generate gas and cause the protective film to peel off from the surface of the wafer, and then lifting and removing the film using an adsorption member (See Sect. 0037). Furthermore, Kiyota discloses a dedicated module (66) for removing a protective film and an adsorption member (662) configured to adsorb onto the surface of the protective film and remove it from the wafer surface (See Sect. 0062) ad film forming apparatus modules (51-53) apply hardener layers (11, 12) to form protective films on the wafer surface (See Sect. 0015-0017), planarization apparatus (56). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kumar to incorporate the protective film forming, grinding and protective film removing apparatus of Kiyota in order to enable thinning of chips by back surface grinding while the chips are held on the electrostatic carrier, without damaging the chip surfaces facing the attraction surface of the carrier.
Referring to claim 4. Kumar in view of Kiyota discloses the system as described above as applied to claim 3. Kumar does not disclose a transferring apparatus configured to transfer the chip between the first electrostatic carrier and a second electrostatic carrier, wherein the transferring apparatus comprises dual carrier holders and dual power supplies configured such that the two carriers face each other. Kiyota discloses a complete semiconductor processing sequence in which wafers are transferred between multiple electrostatic support carriers at different processing stages, and further the transfer between first and second ESC plates (See Sects. 0025-0026, Fig. 6-7), dual carrier attachment modules via ESC plate attachment/detachment modules (65, 74)(located in processing block B2) enable sequential attachment to first ESC plate and detachment followed by attachment to second ESC plate (Sects. 0022-0026, Fig. 26) and discloses that the processing apparatus is configured so that wafers move from one ESC plate to another in a staged transfer, with each carrier positioned to face the loading/unloading stations (See Sect. 0025, Figs. 26-27). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine Kumar’s dual-platform system with the loading plateform and bonding platform with carriers face each other for die transfers with Kiyota’s transfer mechanicals between first and second electrostatic carriers, so that the transfer apparatus is able to have controlled and repeatable movement of chips between processing stages (film formation, grinding, bonding) without manual intervention which would improve throughput and consistency.
Referring to claim 11. Kumar discloses the system as described above as set forth above as applied to claims 1-3, 10. However, Kumar discloses the control terminal (contact pads 116, 118) disposed on the bottom surface (114) of body (110) (¶0021) not on the attraction side. Kiyota discloses ESC plates with integrated surface-mounted control connections positioned for convenience and operational access. Additionally, positioning control terminals on the attraction surface side is a predictable design choice to reduce the internal wiring complexity and maintain the electrode to terminal connection efficiency within a single side of the main body. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to position the control terminal on the attraction surface side of the electrostatic carrier as a design optimization, which simply would have involved relocating the control terminal to the same side as the attraction surface side, which would have been done to reduce wiring complexity and parasitic resistance, resulting in improved electrical efficiency and manufacturing.
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TERRELL H MATTHEWS/Primary Examiner, Art Unit 3653
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