Prosecution Insights
Last updated: July 17, 2026
Application No. 18/710,293

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE

Non-Final OA §102§103§112
Filed
May 15, 2024
Priority
Nov 18, 2021 — DE 10 2021 130 173.4 +1 more
Examiner
CHOU, SHIH TSUN A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ams-osram AG
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
357 granted / 466 resolved
+8.6% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
37 currently pending
Career history
500
Total Applications
across all art units

Statute-Specific Performance

§103
81.9%
+41.9% vs TC avg
§102
7.3%
-32.7% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 466 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 14-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 14 recites these limitations: “wherein the cover element is in direct mechanical contact with the side wall in at least one adhesion region and adheres directly to the housing body in the at least one adhesion region, wherein the housing body has at least one anchoring structure configured to reduce a delamination tendency of the cover element from the housing body in the at least one adhesion region, and wherein the anchoring structure comprises a roughening and/or at least one pillar element located on a bottom surface of the cavity”. Here, since the cover element is in direct mechanical contact with the side wall in at least one adhesion region, the at least one adhesion region is part of the sidewall. Meanwhile, the at least one anchoring structure is in the at least one adhesion region, that is, the at least one anchoring structure is part of the sidewall. It is not clear how the anchoring structure can include an element located on a bottom surface, which is different from the side wall. Claim 18 recites the limitation “wherein the housing body comprises a plastic material, and wherein the roughening is located at least on all surfaces of the plastic material, which are in direct mechanical contact with the cover element”. As discussed above with claim 14, it is not clear how the anchoring structure can include a part that is not only on the side wall of the housing body. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 14-18 and 22, as so far as understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2009/0134408). Regarding claim 14, Park discloses, in FIGS. 1-3 and in related text, an electronic device comprising: a housing body (260) with a cavity (250) in which an electronic semiconductor chip (420) is mounted; and a cover element (600) arranged in the cavity and covering the semiconductor chip, wherein the cavity has a side wall (210), which faces the semiconductor chip, and which surrounds the semiconductor chip in a lateral direction, wherein the cover element is in direct mechanical contact with the side wall in at least one adhesion region (side wall 210) and adheres directly to the housing body in the at least one adhesion region, wherein the housing body has at least one anchoring structure (230, 240) configured to reduce a delamination tendency of the cover element from the housing body in the at least one adhesion region, and wherein the anchoring structure comprises a roughening (uneven surfaces) and/or at least one pillar element located on a bottom surface of the cavity (see Park, [0003], [0037]-[0042]). Regarding claim 15, Park discloses the device of claim 14. Park discloses wherein the at least one adhesion region (side wall 210) completely surrounds the semiconductor chip (420) in the lateral direction (see Park, FIGS. 1-3). Regarding claim 16, Park discloses the device of claim 14. Park discloses wherein the anchoring structure (230, 240) surrounds the semiconductor chip (420) in the lateral direction (see Park, FIGS. 1-3). Regarding claim 17, Park discloses the device of claim 14. Park discloses wherein the anchoring structure (230, 240) comprises at least one depression and/or elevation (protrusion) in the side wall (210) of the cavity (see Park, FIG. 3, [0037], [0042]). Regarding claim 18, Park discloses the device of claim 14. Park discloses wherein the housing body (260) comprises a plastic material (polymer resin), and wherein the roughening is located at least on all (side) surfaces (210) of the plastic material, which are in direct mechanical contact with the cover element (600) (see Park, FIG. 3, [0038], [0063]). Regarding claim 22, Park discloses the device of claim 14. Park discloses wherein the anchoring structure (230, 240) comprises at least one groove (between 230, 240) extending in the side wall (210) in the lateral direction (see Park, FIGS. 1-3). Claims 14-18, 20-21 and 23, as so far as understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishijima (US 2014/0191278). Regarding claim 14, Nishijima discloses, in FIGS. 1A-1B and in related text, an electronic device comprising: a housing body (101) with a cavity in which an electronic semiconductor chip (103) is mounted; and a cover element (104) arranged in the cavity and covering the semiconductor chip, wherein the cavity has a side wall, which faces the semiconductor chip, and which surrounds the semiconductor chip in a lateral direction, wherein the cover element is in direct mechanical contact with the side wall in at least one adhesion region (sidewall portion 101a) and adheres directly to the housing body in the at least one adhesion region, wherein the housing body has at least one anchoring structure (protruding portion 101c) configured to reduce a delamination tendency of the cover element from the housing body in the at least one adhesion region, and wherein the anchoring structure comprises a roughening (uneven surface) and/or at least one pillar element located on a bottom surface of the cavity (see Nishijima, [0033], [0042], [0070]). Regarding claim 15, Nishijima discloses the device of claim 14. Nishijima discloses wherein the at least one adhesion region (sidewall portion 101a) completely surrounds the semiconductor chip (103) in the lateral direction (see Nishijima, FIGS. 1A-1B). Regarding claim 16, Nishijima discloses the device of claim 14. Nishijima discloses wherein the anchoring structure (protrusion 101a) surrounds the semiconductor chip (103) in the lateral direction (see Nishijima, FIG. 1B). Regarding claim 17, Nishijima discloses the device of claim 14. Nishijima discloses wherein the anchoring structure (protrusion 101a) comprises at least one depression and/or elevation in the side wall of the cavity (see Nishijima, FIG. 1B, [0034]). Regarding claim 18, Nishijima discloses the device of claim 14. Nishijima discloses wherein the housing body (including side wall portion 101a) comprises a plastic material (resin), and wherein the roughening (protrusion 101c) is located at least on all surfaces (side wall) of the plastic material, which are in direct mechanical contact with the cover element (104) (see Nishijima, FIG. 1B, [0034]). Regarding claim 20, Nishijima discloses the device of claim 14. Nishijima discloses wherein the anchoring structure (protrusion 101c) comprises at least one web extending on the side wall in a vertical direction (see Nishijima, FIG. 1B). Regarding claim 21, Nishijima discloses the device of claim 14. Nishijima discloses wherein the anchoring structure (protrusion 101c) comprises at least one web extending on the side wall in the lateral direction (see Nishijima, FIG. 1A). Regarding claim 23, Nishijima discloses the device of claim 14. Nishijima discloses wherein the anchoring structure (protrusion 101c) comprises a plurality of island-shaped elevations and/or blind-hole-like depressions arranged in a bead-chain-like manner in the lateral direction (see Nishijima, FIG. 1A). Claims 14-17, as so far as understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su (US 2006/0102918). Regarding claim 14, Su discloses, in FIGS. 4-5 and in related text, an electronic device comprising: a housing body (42, 44) with a cavity in which an electronic semiconductor chip (46) is mounted; and a cover element (52) arranged in the cavity and covering the semiconductor chip, wherein the cavity has a side wall, which faces the semiconductor chip, and which surrounds the semiconductor chip in a lateral direction, wherein the cover element is in direct mechanical contact with the side wall in at least one adhesion region (side wall) and adheres directly to the housing body in the at least one adhesion region, wherein the housing body has at least one anchoring structure (52) configured to reduce a delamination tendency of the cover element from the housing body in the at least one adhesion region, and wherein the anchoring structure comprises a roughening (uneven surface) and/or at least one pillar element located on a bottom surface of the cavity (see Su, [0002], [0020]-[0021], [0025]). Regarding claim 15, Su discloses the device of claim 14. Su discloses wherein the at least one adhesion region (side wall) completely surrounds the semiconductor chip (46) in the lateral direction (see Su, FIGS. 4-5). Regarding claim 16, Su discloses the device of claim 14. Su discloses wherein the anchoring structure (54) surrounds the semiconductor chip (46) in the lateral direction (see Su, FIGS. 4-5). Regarding claim 17, Su discloses the device of claim 14. Su discloses wherein the anchoring structure (54) comprises at least one depression and/or elevation in the side wall of the cavity (see Su, FIG. 5, [0020]-[0021]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 24, as so far as understood, is rejected under 35 U.S.C. 103 as being unpatentable over Nishijima, in view of Tsuyuki (US 2024/0047231). Regarding claim 24, Nishijima discloses the device of claim 14. Nishijima discloses a method for manufacturing the electronic device according to claim 14, the method comprising: forming the housing body with the cavity by a molding process; producing the anchoring structure by the molding process, wherein a film-assisted molding process with a film (mold release sheet) is used, and wherein the anchoring structure comprises the roughening formed by the film, mounting the electronic semiconductor chip in the cavity; and filling a covering material into the cavity to form the cover element (see Nishijima, [0094]-[0099]). Nishijima does not explicitly disclose using a molding tool. Tsuyuki teaches a molding tool (601) (see Tsuyuki, FIG. 5, [0046]). Nishijima and Tsuyuki are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Nishijima with the features of Tsuyuki because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nishijima to include a molding tool, as taught by Su, to provide a vacuum mechanism (see Su, [0046]-[0047]). Claim 26, as so far as understood, is rejected under 35 U.S.C. 103 as being unpatentable over Su, in view of Tsuyuki (US 2024/0047231) and Isokawa (US 2003/0025117). Regarding claim 26, Su discloses the device of claim 14. Su discloses a method for manufacturing the electronic device according to claim 14, the method comprising: forming the housing body with the cavity by molding process; producing the anchoring structure (54); mounting the electronic semiconductor chip (45) in the cavity; and filling a covering material (52) into the cavity to form the cover element (see Su, FIG. 5, [0021]). Su does not explicitly disclose using a molding tool. Tsuyuki teaches a molding tool (601) (see Tsuyuki, FIG. 5, [0046]). Su and Tsuyuki are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su with the features of Tsuyuki because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Su to include a molding tool, as taught by Su, to provide a vacuum mechanism (see Su, [0046]-[0047]). Su does not explicitly disclose producing the anchoring structure by an etching process or by a laser structuring or by attaching one or more pre-fabricated anchoring elements to the housing body by the molding process. Isokawa teaches producing the anchoring structure (indentations) by an etching process (see Isokawa, [0031]). Thus Isokawa teaches producing the anchoring structure by an etching process or by a laser structuring or by attaching one or more pre-fabricated anchoring elements to the housing body by the molding process. Su and Isokawa are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su with the features of Isokawa because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Su to include producing the anchoring structure by an etching process or by a laser structuring or by attaching one or more pre-fabricated anchoring elements to the housing body by the molding process, as taught by Isokawa, because it is use of known technique to improve similar devices in the same way. See MPEP § 2143. Allowable Subject Matter Claims 19, 25 and 27 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, Su, discloses wherein the side wall has an upper region projecting above the semiconductor chip in a vertical direction, wherein the anchoring structure is arranged only in an upper part of the upper region as viewed from the semiconductor chip in the vertical direction. The prior art of records, individually or in combination, do not disclose nor teach “wherein the upper part occupies a proportion of less than or equal to 80% of the upper region from an top edge of the side wall” in combination with other limitations as recited in claim 19. The prior art of records, individually or in combination, do not disclose nor teach “wherein the covering material has a viscosity and the anchoring structure has a structure size, and wherein the structure size and the viscosity are adapted to each other such that the anchoring structure is completely in direct contact with the finished cover element” in combination with other limitations as recited in claim 25. The prior art of records, individually or in combination, do not disclose nor teach “wherein the covering material has a viscosity and the anchoring structure has a structure size, and wherein the structure size and the viscosity are adapted to each other such that the anchoring structure is completely in direct contact with the finished cover element” in combination with other limitations as recited in claim 27. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
94%
With Interview (+17.5%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 466 resolved cases by this examiner. Grant probability derived from career allowance rate.

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