DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 32 is objected to because of the following informalities: In claim 32, line 2, the recitation of “contracts” should be changed to “contacts”, for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19-35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2021/0249558).
Regarding claim 19, Tsai et al. discloses, as shown in Figures 1-7, a wafer comprising:
a plurality of optoelectronic components (1); and
means for testing at least one of the optoelectronic components for at least one parameter,
wherein the plurality of optoelectronic components comprises at least one light-emitting layer (123), which is arranged between an insulating layer (50) and a light emission layer (121),
wherein the insulating layer of at least one optoelectronic component comprises a first contact (30) and a second contact (20) arranged on the light emission layer of the at least one optoelectronic component, and
wherein the second contact is arranged outside a light emission surface of the at least one optoelectronic component.
Regarding claim 20, Tsai et al. discloses the means for testing comprise contact elements with which the at least one optoelectronic component is suppliable with an electric current [0034].
Regarding claim 21, Tsai et al. discloses the wafer comprises a plurality of wafer elements, each of which comprises an optoelectronic component and a test structure (60a,60b).
Regarding claim 22, Tsai et al. discloses the optoelectronic component is electrically coupled to the test structure via an anchor structure (401a,401b) [Figures 4A-4D].
Regarding claim 23, Tsai et al. discloses that the optoelectronic components comprise a plurality of layers (121,122,123), which are arranged on a production substrate in a stacked manner, wherein each optoelectronic component is separated in some regions from a surrounding material of the test structure by a trench (ISO, Figure 2), and wherein at least one of the optoelectronic components is connected to surrounding regions of the test structure via the anchor structure (401a,401b) [Figures 4A-4D].
Regarding claim 24, Tsai et al. discloses the anchor structure comprises at least one conductive or semiconductive layer (401a,401b, [0034] of the plurality of layers.
Regarding claim 25, Tsai et al. discloses the at least one of the plurality of layers with which the optoelectronic component is connected to surrounding regions of a wafer element comprises at least parts of the light-emitting layer [Figures 2 and 6].
Regarding claim 26, Tsai et al. discloses the at least one of the plurality of layers with which the optoelectronic component is connected to surrounding regions of a wafer element comprises the light emission layer, which is conductive
Regarding claim 27, Tsai et al. discloses the light emission layer comprises an N-contact [0023].
Regarding claim 28, Tsai et al. discloses the light emission layer consists of a conductive or semiconductive material and the N-contact is arranged at it.
Regarding claim 29, Tsai et al. discloses the insulating layer (50) comprises a conductive or semiconductive region as a P-contact (30) [0023].
Regarding claim 30, Tsai et al. discloses, as shown in Figures, an arrangement for testing optoelectronic components comprising:
at least one wafer element comprising at least one optoelectronic component and means for testing the at least one optoelectronic component (1) for at least one parameter, wherein the at least one optoelectronic component comprises at least one light-emitting layer (123), which is arranged between an insulating layer (50) and a light emission layer (121), wherein the insulating layer of the at least one optoelectronic component comprises a first contact (30) and a second contact (20) arranged on the light emission layer of the at least one optoelectronic component, wherein the second contact is arranged outside a light emission surface of the at least one optoelectronic component; and
a test wafer (60a,60b) having at least one electrical connection means conductively connected to one of the contacts of at least one of the optoelectronic components.
Regarding claim 31, Tsai et al. discloses the at least one electrical connection means contacts a contact surface in the insulating layer.
Regarding claim 32, Tsai et al. discloses the at least one electrical connection means contracts the contact surface in the insulating layer by a solder (32) [Figure 6].
Regarding claim 33, Tsai et al. discloses, as shown in Figures, a method for testing portions of a wafer comprising:
providing at least one wafer element (10) comprising at least one optoelectronic component (1) and means for testing the at least one optoelectronic component for at least one parameter, wherein the at least one optoelectronic component comprises at least one light-emitting layer (123), which is arranged between an insulating layer (50) and a light emission layer (121), wherein the insulating layer of the at least one optoelectronic component comprises a first contact (30) and a second contact (20) arranged on the light emission layer of the at least one optoelectronic component, wherein the second contact is arranged outside a light emission surface of the at least one optoelectronic component;
separating a portion of the wafer elements to form a test array (Z1 - Z4, Row1 – Row3);
connecting at least one of the wafer elements of the test array to a test substrate (60a,60b);
powering at least one of the optoelectronic components of the wafer elements [0034],[0037]-[0038],[0044]; and
measuring the at least one parameter of the at least one powered optoelectronic component [0048]-[0049].
Regarding claim 34, Tsai et al. discloses the method further comprising removing a production substrate (10) before separating the portion of the at least one wafer element [0059]-[0060].
Regarding claim 35, Tsai et al. discloses the method further comprising applying a solder (32) to a conductive substrate for connecting the at least one wafer element of the test array to the test substrate [Figure 6].
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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