Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/15/2024, 5/16/2024, and 4/8/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the positional relationship of the portion in which the “recessed portions are different in at least one of a density, a width, a depth, and a shape in the recessed portion layer” and “at least one of a position of a sub-substrate which is mounted on the semiconductor substrate, a wire density of a wire which is formed in the semiconductor substrate, and an arrangement density of a through electrode which is formed in the semiconductor substrate.” The current language used to describe the positional relationship is “according to . . . a position of” which has no definite meaning when referring to positional relationships. For the purposes of this action, “according to . . . a position of” will be interpreted as “in a region directly overlapping, in a direction perpendicular to the formation surface of the semiconductor element, at least one of a sub-substrate . . .”
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 refers to “a wire density of a wire which is formed in the semiconductor substrate.” It is indefinite whether this refers to a mass density per unit volume of the wire itself or the distribution density of wire in a particular region (i.e., the length of wire that is disposed in a particular region). As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For the purposes of examination, the claim will be interpreted as referring to the distribution density of wire in a particular region (i.e., the length of wire that is disposed in a particular region).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The examiner notes that translations of foreign patent literature are relied upon in this office action. All quotations and figure numbers of foreign patent literature referenced in this office action refer to the translations thereof attached to this office action.
Claim(s) 1-4, 6-7, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto (JP 2012146734 A).
Regarding claim 1, Matsumoto discloses, in FIG. 1A, a semiconductor device, comprising: a semiconductor substrate 1 on which a semiconductor element is formed (Abstract states: “semiconductor circuit formation layer 2 formed on a surface of a semiconductor substrate 1”); a recessed portion layer (layer on the ‘bottom’ portion of the semiconductor substrate 1 - as it is oriented in FIG. 1A - into which “recesses” 7 are etched) including recessed portions 7 that have openings in a same surface other than a formation surface of the semiconductor element and that are unevenly arranged (see uneven arrangements of “recesses” 21, 22, 23, 24, 25, 26 in FIGs 3a, 3b, 4a, 4b, 5a, and 5b); and a filling film (“metal film”) 6 that fills the recessed portions.
Regarding claim 2, as explained above Matsumoto discloses “metal film” 6, metals are inorganic, and this is therefore an inorganic film. In addition, Embodiment 1 paragraph 3 states “. . . a metal film 6 made of aluminum (Al) or aluminum nitride (AlN) is formed . . .” The examiner notes that an AlN film is also an inorganic film.
Regarding claim 3, Matsumoto further discloses, in Embodiment 1 Paragraph 3, “. . . in the semiconductor device according to the present embodiment, a groove-shaped recess 7 is formed . . .” The examiner notes that this discloses that the recessed portions are grooves.
Regarding claim 4, Matsumoto further discloses, in FIGs. 3a, 3b, 4a, and 4b, differing densities of recessed portions in various regions of the recessed portion layer.
Regarding claim 6, Matsumoto further discloses, in FIG. 3B, a lattice-like pattern of recessed portions. In FIG. 5b, Matsumoto discloses a circular pattern of recessed portions. In. FIG. 3a, Matsumoto teaches an isolated pattern of recessed portions (the recessed portions are isolated from one another).
Regarding claim 7, Matsumoto further discloses, in FIG. 1a, that the recessed portion layer is formed on a surface opposite to the surface on which the semiconductor element (on layer 2, see above) is found.
Regarding claim 11, Matsumoto further discloses, in FIGs. 5a and 5b, that the recessed potions are separated from an end of the semiconductor substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (JP 2012146734 A).
Regarding claim 5, as explained above, Matsumoto teaches the limitations of claim 5, Matsumoto further teaches, in Embodiment 1 paragraph 9 “In the present invention. . . the density of the recesses 7 is increased at the central portion of the semiconductor substrate 1 and decreased at the peripheral portion . . . A region having a high density of recesses in the semiconductor substrate has a small apparent elastic modulus and can be easily deformed, and a region having a low density has a large apparent elastic modulus and is difficult to deform. Therefore, if the recesses are arranged at a higher density in a region where the greater stress is to be generated (the central portion of the semiconductor substrate) to increase the degree of stress relaxation, the stress distribution in the semiconductor substrate can be made uniform.” The examiner also notes that the central region of semiconductor substrate 1 directly overlaps, in a direction perpendicular with the formation surface of the semiconductor substrate, with a position of a “wiring board body” (analogous to a sub-substrate) mounted on the semiconductor substrate (see FIG. 1a).
It would have been obvious to one having ordinary skill in the art at the effective filing date to form the recessed portions in a greater (different) density in a region directly overlapping, in a direction perpendicular to the formation surface of the semiconductor element, the position of a sub-substrate, at least one of a mounted sub-substrate, dense wire(s) in the substrate, or dense electrode(s) mounted on the substrate. One having ordinary skill in the art is motivated to do so in order to reduce the stress on the substrate in those regions (evening the stress load across the substrate), as densities of sub-substrates, wires, and through electrodes have weight and are well known to increase stress on a substrate (further, “Making the stress distribution applied to the semiconductor substrate uniform improves the uniformity of the distribution in the semiconductor substrate (chip) of the transistor characteristics constituting the semiconductor circuit,” Matsumoto, Embodiment 1 paragraph 10).
Regarding claim 8, Matsumoto further teaches, in FIG. 7a, an embodiment in which “hard mask” (protective film, as it is disposed to protect the substrate) 42 is formed over the substrate and the recessed portion layer (in which recessed portions 7a are formed) is formed in the protective film. In this particular embodiment, Matsumoto does not explicitly teach a filling film filling the recessed portions 7a.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device of this embodiment taught by Matsumoto such that the filling film taught by Matsumoto in other embodiments fills the recessed portions 7a of the recessed portion layer. One having ordinary skill in the art is motivated to do so in because, for example “Since the metal film 6 has a higher thermal conductivity than the semiconductor substrate 1, heat generated during operation of the semiconductor device can be efficiently released . . . formation of the recess 7 increases the surface area of the metal film 6 and improves the heat dissipation efficiency . . . Therefore, the malfunction of the semiconductor circuit due to the temperature rise can be suppressed” (Matsumoto, Embodiment 1 paragraph 13).
Regarding claim 9, Matsumoto teaches the limitations of claim 1, Matsumoto further teaches, in FIG. 8D, “support substrate” 40 which supports the semiconductor substrate, although this is removed in subsequent manufacturing steps (see Embodiment 2 paragraph 9 “Next, the adhesive layer 41 is dissolved to separate the support substrate 40 . . .”).
Matsumoto does not explicitly teach that the recessed portion layer is formed in the support substrate.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Matsumoto such that the support substrate remains and recessed portion layers are formed in the support substrate. One having ordinary skill in the art is motivated to retain the support substrate so that it may continue to support the semiconductor substrate, and is motivated to form the recessed portion layer to garner the stress distribution benefits taught by Matsumoto above, increasing device robustness. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 10, Matsumoto teaches, in Embodiment 1 paragraph 18: “When the groove pattern is formed on the back surface of the semiconductor substrate 1 as shown in FIG. 3A to FIG. 5B, the groove width is specifically set to 10 μm to 100 μm . . . The thickness is preferably about 1/30 to 1/3 of the thickness (10 μm to 100 μm if the thickness of the semiconductor substrate 1 is about 300 μm).” The examiner notes that while the same paragraph states “ . . . the groove depth is set to the depth of the semiconductor substrate 1 . . .,” FIGS. 1a, 7a, 7b, 8d, 9a, 9b, 9c (all figures showing cross-sections of grooves) clearly show that the grooves do not go all the way through the substrate, indicating that “depth” in this context does not refer to a dimension perpendicular to the surface of the substrate (and rather, “thickness” refers to this dimension).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Matsumoto such that the recessed portions have a width that is greater than 0 pm but is equal to or less than 10 μm, and has a depth that is greater than 0 μm but is equal to or less than 30 μm. One having ordinary skill it the art is motivated to do so in order to, for example, provide sufficiently wide and deep recessed portions in a smaller semiconductor substrate (in which a lower end of the range taught by Matsumoto - greater than 0 and up to 30 μm - is desirable, due to reduced depth and width available to form the recessed portions). See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); also see In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); also see MPEP 2144.05 (I).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izumi (US 20100109114 A1) in view of Matsumoto (JP 2012146734 A).
Regarding claim 12, Izumi teaches, in FIG. 1B , a semiconductor device comprising a semiconductor substrate 11 on which a “sensor circuit” 20 (semiconductor element) is formed, a recessed potion layer (i.e., the layer of the semiconductor substrate 11 in which the “trench” mentioned in the following statement from [0065] is formed: “. . . back contact 50 is provided by forming a trench . . .”) which is filled with “insulation film” (filling film) 19. Izumi further teaches “plating film 33 made of Cu” ([0080]) which conformally forms a through electrode which passes through the semiconductor substrate 11 and a rear-surface wire that is formed on a surface of the semiconductor substrate opposite to the surface on which the semiconductor element is formed. The examiner notes that this conformal formation means that the through electrode and rear-surface wire components are connected.
Izumi does not teach multiple recessed portions that have openings in a same surface.
Matsumoto teaches, in FIG. 1A, a semiconductor device, comprising: a semiconductor substrate 1 on which a semiconductor element is formed (Abstract states: “semiconductor circuit formation layer 2 formed on a surface of a semiconductor substrate 1”); a recessed portion layer (layer on the bottom portion of the semiconductor substrate 1 - as it is oriented in FIG. 1A - into which “recesses” 7 are etched) including recessed portions 7 that have openings in a same surface other than a formation surface of the semiconductor element and that are unevenly arranged (see uneven arrangements of “recesses” 21, 22, 23, 24, 25, 26 in FIGs 3a, 3b, 4a, 4b, 5a, and 5b); and a filling film (“metal film”) 6 that fills the recessed portions.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Izumi such that a plurality of recesses are implemented unevenly, as taught by Matsumoto. One having ordinary skill in the art is motivated to do so because, for example, “. . .if the recesses are arranged at a higher density in a region where the greater stress is to be generated . . . to increase the degree of stress relaxation, the stress distribution in the semiconductor substrate can be made uniform . . . Making the stress distribution applied to the semiconductor substrate uniform improves the uniformity of the distribution in the semiconductor substrate (chip) of the transistor characteristics constituting the semiconductor circuit” (Matsumoto, Embodiment 1 paragraphs 9 and 10). The examiner notes that “higher density” arrangements in the “greater stress” region amounts to “unevenly arranged” recesses.
Regarding claim 13, Izumi further teaches, in FIG. 1B, that the filling film 19 also comprises portions that insulate the rear surface wire from the semiconductor substrate (as it is an “insulation film” disposed between the rear surface wire and the semiconductor substrate). The examiner notes that the insulating film and the filling film share the same materials, as they are made of the same film (see also [0063]). See annotated FIG. 1B below.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sano (US 20110169118 A1) in view of Matsumoto (JP 2012146734 A).
Regarding claim 14, as shown above, Matsumoto teaches the limitations of claim 1. Matsumoto does not teach that the semiconductor element is a back-illuminated solid state imaging element.
Sano teaches, in FIG. 23A, a semiconductor device, comprising: a semiconductor substrate 1, [0162] states “elements and wiring 20 electrically connected to the elements are formed . . . on a side of the other surface (bottom surface) of the semiconductor substrate 1” (a semiconductor element is formed on the substrate); a recessed portion layer 5 including recessed portions that have openings in a same surface other than a formation surface of the semiconductor element. In addition, [0162] further states “FIG. 23A, . . . is a back-side illumination solid-state imaging device.”
Sano does not teach that the recessed portions are unevenly arranged or a filling film that fills the recessed portions.
Matsumoto teaches, in FIG. 1A, a semiconductor device, comprising: a semiconductor substrate 1 on which a semiconductor element is formed (Abstract states: “semiconductor circuit formation layer 2 formed on a surface of a semiconductor substrate 1”); a recessed portion layer (layer on the bottom portion of the semiconductor substrate 1 - as it is oriented in FIG. 1A - into which “recesses” 7 are etched) including recessed portions 7 that have openings in a same surface other than a formation surface of the semiconductor element and that are unevenly arranged (see uneven arrangements of “recesses” 21, 22, 23, 24, 25, 26 in FIGs 3a, 3b, 4a, 4b, 5a, and 5b); and a filling film (“metal film”) 6 that fills the recessed portions.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Sano such that the recessed portions are unevenly arranges, and such that a filling film fills the recessed portions, as taught by Matsumoto. One having ordinary skill in the art is motivated to do so because “. . .if the recesses are arranged at a higher density in a region where the greater stress is to be generated . . . to increase the degree of stress relaxation, the stress distribution in the semiconductor substrate can be made uniform . . . Making the stress distribution applied to the semiconductor substrate uniform improves the uniformity of the distribution in the semiconductor substrate (chip) of the transistor characteristics constituting the semiconductor circuit” (Matsumoto, Embodiment 1 paragraphs 9 and 10)), and to fill the recesses with a filling film because “Since the metal film 6 has a higher thermal conductivity than the semiconductor substrate 1, heat generated during operation of the semiconductor device can be efficiently released . . . formation of the recess 7 increases the surface area of the metal film 6 and improves the heat dissipation efficiency . . . Therefore, the malfunction of the semiconductor circuit due to the temperature rise can be suppressed” (Matsumoto, Embodiment 1 paragraph 13). The examiner notes that “higher density” arrangements in the “greater stress” region amounts to “unevenly arranged” recesses.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Brouillette (US 5913125 A) – “Method of controlling Stress in a Film” – recesses formed in substrate 22 and filled with “layers” 24 and 26 (see FIG. 8); see paragraph 10 for brief discussion of utility.
Chong (US 11164749 B1) – “Warpage Reduction” – method of reducing warpage in a substrate by etching “trenches” into them and depositing “stressed materials” into the trenches (see FIGs. 3A – 3D); see paragraphs 2-3 for brief discussion of utility.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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