Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/16/2024 has been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 05/16/2024 is noted by the Examiner.
Title Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 discloses the limitation “…a plus-side detection wire connected between a plus input terminal of the differential amplifier and one end of both ends at which the detector is connected to the path …” in lines 6-7 or Claim 11. It is not clear if the underlined limitation refers to the same “path of current in the electric circuit”, “path voltage in the electric circuit”; both disclosed earlier in Claim 11; or if it refers to a different “path”; therefore, please provide clarification with regards to the underlined limitation in question in order to avoid confusion.
Claim 12 discloses the limitation “…a plus-side detection wire connected between a plus input terminal of the differential amplifier and one end of both ends at which the detector is connected to the path …” in lines 6-7 or Claim 12. It is not clear if the underlined limitation refers to the same “path of current in the electric circuit”, “path voltage in the electric circuit”; both disclosed earlier in Claim 12; or if it refers to a different “path”; therefore, please provide clarification with regards to the underlined limitation in question in order to avoid confusion.
Claim 13 discloses the limitation “…a plus-side detection wire connected between a plus input terminal of the differential amplifier and one end of both ends at which the detector is connected to the path …” in lines 6-7 or Claim 13. It is not clear if the underlined limitation refers to the same “path of current in the electric circuit”, “path voltage in the electric circuit”; both disclosed earlier in Claim 13; or if it refers to a different “path”; therefore, please provide clarification with regards to the underlined limitation in question in order to avoid confusion.
Claims 14-19 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit rejected Claim 11.
Claims 20, 22, 25, 27 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit rejected Claim 12.
Claims 21, 23, 26, 28 and 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit rejected Claim 13.
Please make the proper corrections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11, 13-16, 21, 23, 24, 26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al. JP 2020046207 (Provided by Applicant; Hereinafter Kikuchi) in view of Hirasawa et al. JP 2015017832 (Provided by Applicant; Hereinafter Hirasawa).
Regarding claim 11, Kikuchi teaches a detection circuit (Figs. 1-8; [0014-0037]; current detection device) of which wiring is made at a multilayer board having at least two layers (Figs. 1-8; [0014-0037]; plurality of insulating layers; From [0014]: “A according to the present embodiment includes a plurality of insulating layers, for example, a plurality of insulating layers formed of a ceramic material mainly containing barium oxide, silica, alumina or the like. , 17, 21 and 31 are sequentially laminated from the bottom and fired to form a ceramic laminate. In addition, the present invention may be configured by a resin multilayer substrate in which a resin-based substrate is multilayered in addition to the ceramic material.”), the detection circuit comprising:
a detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) interposed on a path of current or voltage in an electric circuit (Figs. 1-8; [0014-0037]; shunt resistor, 1);
a differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) which outputs voltage according to the current or the voltage (Figs. 1-8; [0014-0037]; amplification circuit, 65) detected by the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1);
a plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) connected between a plus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) and one end of both ends at which the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) is connected to the path (Figs. 1-8; [0014-0037]; voltage detection vias, 19);
a minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) connected between a minus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) and another end of both ends (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2);
at least one first detection wire (Figs. 1-8; [0014-0037]; current vias; 18) connected in parallel to at least a part of the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) between the one end of the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) and the plus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65); and
at least one second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) connected in parallel to at least a part of the minus-side detection wire Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) between the other end of the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) and the minus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65).
Kikuchi does not specifically teach at the same layer of the multilayer board, each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be adjacent to, in a direction parallel to a surface of the multilayer board, any of detection wires included in the minus-side detection wire and the second detection wire, and at different layers of the multilayer board, each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be opposed to, in a direction perpendicular to the surface of the multilayer board, any of detection wires included in the second detection wire and the minus-side detection wire.
However, Hirasawa does teach at the same layer of the multilayer board (Figs. 1-10; [0010-0033]), each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be adjacent to, in a direction parallel to a surface of the multilayer board (Figs. 1-10; [0010-0033]), any of detection wires included in the minus-side detection wire and the second detection wire (Figs. 1-10; [0010-0033]), and at different layers of the multilayer board (Figs. 1-10; [0010-0033]), each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be opposed to (Figs. 1-10; [0010-0033]), in a direction perpendicular to the surface of the multilayer board (Figs. 1-10; [0010-0033]), any of detection wires included in the second detection wire and the minus-side detection wire (Figs. 1-10; [0010-0033]).
It would have been obvious before the effective filing date of the claimed invention to modify the current detection device of Kikuchi by implementing the teachings of Hirasawa regarding at the same layer of the multilayer board, each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be adjacent to, in a direction parallel to a surface of the multilayer board, any of detection wires included in the minus-side detection wire and the second detection wire, and at different layers of the multilayer board, each detection wire included in the plus-side detection wire and the first detection wire is arranged so as to be opposed to, in a direction perpendicular to the surface of the multilayer board, any of detection wires included in the second detection wire and the minus-side detection wire; in order to “provide a current detection device with a resistor that enables a parasitic inductance of the resistor to be adjusted according to a circuit constant of a low-pass filter” (See Hirasawa; Abstract).
Regarding claim 13, Kikuchi teaches a detection circuit (Figs. 1-8; [0014-0037]; current detection device) of which wiring is made at a board (Figs. 1-8; [0014-0037]; plurality of insulating layers), the detection circuit comprising:
a detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) interposed on a path of current or voltage in an electric circuit (Figs. 1-8; [0014-0037]; shunt resistor, 1);
a differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) which outputs voltage according to the current or the voltage detected by the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1);
a plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) connected between a plus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) and one end of both ends at which the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) is connected to the path (Figs. 1-8; [0014-0037]; voltage detection vias, 19);
a minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) connected between a minus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) and another end of both ends (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2);
at least one first detection wire (Figs. 1-8; [0014-0037]; current vias; 18) connected in parallel to at least a part of the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) between the one end of the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) and the plus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65); and
at least one second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) connected in parallel to at least a part of the minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) between the other end of the detector (Figs. 1-8; [0014-0037]; shunt resistor, 1) and the minus input terminal of the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65), wherein
Kikuchi does not specifically teach at the same surface of the board, a plurality of pairs composed of each detection wire included in the plus-side detection wire and the first detection wire and each detection wire included in the minus-side detection wire and the second detection wire are arranged in parallel, and two, of the detection wires, that are adjacent to each other and are included in two adjacent pairs among the plurality of pairs, are connected to the plus input terminal or the minus input terminal of the differential amplifier.
However, Hirasawa does teach at the same surface of the board (Figs. 1-10; [0010-0033]), a plurality of pairs composed of each detection wire included in the plus-side detection wire and the first detection wire and each detection wire included in the minus-side detection wire and the second detection wire are arranged in parallel (Figs. 1-10; [0010-0033]), and two, of the detection wires, that are adjacent to each other and are included in two adjacent pairs among the plurality of pairs (Figs. 1-10; [0010-0033]), are connected to the plus input terminal or the minus input terminal of the differential amplifier (Figs. 1-10; [0010-0033]).
It would have been obvious before the effective filing date of the claimed invention to modify the current detection device of Kikuchi by implementing the teachings of Hirasawa regarding at the same surface of the board, a plurality of pairs composed of each detection wire included in the plus-side detection wire and the first detection wire and each detection wire included in the minus-side detection wire and the second detection wire are arranged in parallel, and two, of the detection wires, that are adjacent to each other and are included in two adjacent pairs among the plurality of pairs, are connected to the plus input terminal or the minus input terminal of the differential amplifier; in order to “provide a current detection device with a resistor that enables a parasitic inductance of the resistor to be adjusted according to a circuit constant of a low-pass filter” (See Hirasawa; Abstract).
Regarding claim 14, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 11, wherein Kikuchi further teaches wherein each detection wire included in the first detection wire is paired with each detection wire included in the second detection wire, and a total number of the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19; current vias; 18a-2, 18b-2 current vias, 18), the minus-side detection wire, the first detection wire, and the second detection wire is a multiple of 2 (Figs. 1-8; [0014-0037]; voltage detection vias, 19; current vias; 18a-2, 18b-2 current vias, 18).
Regarding claim 15, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 11, wherein Kikuchi further teaches wherein the first detection wire and the second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) are arranged so that output voltage obtained by the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) combining first difference voltage which is a difference between the induced voltages on the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) and the minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) and second difference voltage which is a difference between the induced voltages on the first detection wire and the second detection wire, becomes 0 (Figs. 1-8; [0014-0037]; amplification circuit, 65; current vias; 18).
Regarding claim 16, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 11, wherein Kikuchi further teaches wherein the detector is a resistor (Figs. 1-8; [0014-0037]; shunt resistor, 1), and a value of current or voltage present in a main circuit to which the resistor is electrically connected is detected or measured on the basis of voltage generated between both ends when current flows through the resistor (Figs. 1-8; [0014-0037]; shunt resistor, 1).
Regarding claim 21, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 13, wherein Kikuchi further teaches wherein each detection wire included in the first detection wire is paired with each detection wire included in the second detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19; current vias; 18a-2, 18b-2 current vias, 18), and a total number of the plus-side detection wire, the minus-side detection wire, the first detection wire, and the second detection wire is a multiple of 2 (Figs. 1-8; [0014-0037]; voltage detection vias, 19; current vias; 18a-2, 18b-2 current vias, 18).
Regarding claim 23, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 13, wherein Kikuchi further teaches wherein the first detection wire and the second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) are arranged so that output voltage obtained by the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) combining first difference voltage which is a difference between the induced voltages on the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) and the minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) and second difference voltage which is a difference between the induced voltages on the first detection wire and the second detection wire, becomes 0 (Figs. 1-8; [0014-0037]; amplification circuit, 65; current vias; 18).
Regarding claim 24, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 14, wherein Kikuchi further teaches wherein the first detection wire and the second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) are arranged so that output voltage obtained by the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) combining first difference voltage which is a difference between the induced voltages on the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) and the minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) and second difference voltage which is a difference between the induced voltages on the first detection wire and the second detection wire, becomes 0 (Figs. 1-8; [0014-0037]; amplification circuit, 65; current vias; 18).
Regarding claim 26, , the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 21, wherein Kikuchi further teaches wherein the first detection wire and the second detection wire (Figs. 1-8; [0014-0037]; current vias; 18) are arranged so that output voltage obtained by the differential amplifier (Figs. 1-8; [0014-0037]; amplification circuit, 65) combining first difference voltage which is a difference between the induced voltages on the plus-side detection wire (Figs. 1-8; [0014-0037]; voltage detection vias, 19) and the minus-side detection wire (Figs. 1-8; [0014-0037]; current vias; 18a-2, 18b-2) and second difference voltage which is a difference between the induced voltages on the first detection wire and the second detection wire, becomes 0 (Figs. 1-8; [0014-0037]; amplification circuit, 65; current vias; 18).
Regarding claim 28, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 13, wherein Kikuchi further teaches wherein the detector is a resistor (Figs. 1-8; [0014-0037]; shunt resistor, 1), and a value of current or voltage present in a main circuit to which the resistor is electrically connected is detected or measured on the basis of voltage generated between both ends when current flows through the resistor (Figs. 1-8; [0014-0037]; shunt resistor, 1).
Claim(s) 17 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Hirasawa in further view of Kobayashi et al. JP 2003114243 (Provided by Applicant; Hereinafter Kobayashi).
Regarding claim 17, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 11, but not specifically wherein the detector is a capacitor, and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor.
However, Kobayashi does teach wherein the detector is a capacitor (Fig. 1; [0026-0031]; capacitor circuit, 4; capacitor, C1) and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor (Fig. 1; [0026-0031]; capacitor circuit, 4; capacitor, C1).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Kikuchi and Hirasawa by implementing the teachings of Kobayashi regarding wherein the detector is a capacitor, and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor; in order to “provide a direct-measuring type battery pack voltage detection circuit capable of reducing a bad influence of an invading noise without reducing the short-circuit protection function of a multiplexer” (See Kobayashi; Abstract).
Regarding claim 30, the combination of Kikuchi and Hirasawa teach the detection circuit according to claim 13, but not specifically wherein the detector is a capacitor, and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor.
However, Kobayashi does teach wherein the detector is a capacitor (Fig. 1; [0026-0031]; capacitor circuit, 4; capacitor, C1) and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor (Fig. 1; [0026-0031]; capacitor circuit, 4; capacitor, C1).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Kikuchi and Hirasawa by implementing the teachings of Kobayashi regarding wherein the detector is a capacitor, and a value of current or voltage present in a main circuit to which the capacitor is electrically connected is detected or measured on the basis of voltage stored in the capacitor; in order to “provide a direct-measuring type battery pack voltage detection circuit capable of reducing a bad influence of an invading noise without reducing the short-circuit protection function of a multiplexer” (See Kobayashi; Abstract).
Allowable Subject Matter
Claims 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 18, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 11,
“…connected in series to each phase; an upper arm and a lower arm which alternately perform switching operations using switching elements; a gate driving circuit which turns on or off the switching elements; and a controlling circuitry which controls the gate driving circuit, wherein the detection circuit is connected in series to the switching element for each phase in either the upper arm or the lower arm, and inputs the output of the differential amplifier to the controlling circuitry.”
Regarding claim 19, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 11,
“…connected in series to each phase; a gate driving circuit which turns on or off current flowing through a reactor or smoothing capacitor, using switching elements; and a controlling circuitry which controls the gate driving circuit, wherein the detection circuit is connected in series to the switching element for each phase and inputs the output of the differential amplifier to the controlling circuitry.”
Claim 12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 12, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 12,
“…through-holes or via-holes provided at both ends of each of the plus-side detection wire and the minus-side detection wire arranged at a first layer of the multilayer board, wherein the first detection wire and the second detection wire are arranged at a second layer of the multilayer board electrically connected with the first layer via the through-holes or the via-holes, both ends of the plus-side detection wire are respectively connected to both ends of the first detection wire via the through-holes or the via-holes, both ends of the minus-side detection wire are respectively connected to both ends of the second detection wire via the through-holes or the via-holes, and a pair of wires composed of the first detection wire and the second detection wire have equal lengths and are arranged so as to be point-symmetric with respect to a center of gravity among connection parts where the first detection wire and the second detection wire, and the through-holes or the via-holes, are connected to each other.”
Claims 20, 22, 25, 27 and 29 are also allowed as they further limit allowed claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858