Prosecution Insights
Last updated: August 17, 2026
Application No. 18/711,075

IMAGE SENSOR, CAMERA COMPACT MODULE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING PACKAGING STRUCTURE OF IMAGE SENSOR

Non-Final OA §103
Filed
May 16, 2024
Priority
May 23, 2023 — nonprovisional of PCTCN2023095843
Examiner
CHIN, EDWARD
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
603 granted / 692 resolved
+19.1% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
29 currently pending
Career history
704
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 692 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action This office action is in response to applicant’s communication filed on 05/16/24. Claims 1-17, 19, 22, 23 are pending in this application. Information Disclosure Statement The information disclosure statement filed on 11/18/24, 11/22/24, and 03/05/26 have been received and are being considered. Claim Rejections Under 35 U.S.C. §103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1-10, 22 and 23 is rejected under 35 U.S.C. §103 as being unpatentable over Izuha(CN102738187A) and further in view of Qin (CN105448946A). Regarding claim 1, Izuha discloses a solid-state imaging device and an electronic apparatus of a solid-state imaging device and an electronic device, and discloses an image sensor (see paragraphs 117-159 of the specification, Fig. 12) including a solid-state imaging device body 29 (equivalent to a sensor chip in the present invention) and a packaging structure including: Sealing glass 28b (equivalent to the first transparent substrate in the present invention); An encapsulation assembly for encapsulating the solid imaging device body 29, the encapsulation assembly being arranged on a side of the sealing glass 28b facing the photosensitive area of the solid imaging device body 29, and A dimming lamination film 27 (equivalent to a dimming assembly in the present disclosure) for adjusting the light intensity incident to the photosensitive area of the solid imaging device body 29 is arranged on one side of the sealing glass 28b, and an orthographic projection of the dimming lamination film 27 onto the sealing glass 28b covers an orthographic projection of the photosensitive area of the solid imaging device body 29 onto the sealing glass 28b. However, Izuha does not disclose that the orthographic projection of the package assembly onto the first transparent substrate does not overlap with the orthographic projection of the photosensitive region of the sensor chip onto the first transparent substrate. However, Qin (CN105448946A) discloses an image sensor chip packaging structure and implementation process, and specifically discloses (see paragraphs 0064-0137 of the specification, FIGS. 1-20) that the orthographic projection of the package assembly onto the transparent substrate 105 (equivalent to the first transparent substrate of the present invention) does not overlap with the orthographic projection of the photosensitive region 100a of the sensor chip 104 onto the transparent substrate 105. Izuha and Qin are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Qin with Izuha. Izuha and Qin may be combined by forming the device of Qin in accordance with the projection process disclosed in Izuha. One having ordinary skill in the art would be motivated to combine Izuha and Qin in order to reduce processing defects, see paras [0064]-[0137] of Izuha. Regarding claim 2, Qin and Izuha disclose the features of claim 1, Izuha further discloses (see paragraphs 117-159 of the specification, Figure 12): A dimming lamination film 27 is arranged on the same side of the sealing glass 28b as the encapsulation assembly, the dimming lamination film 27 including a second transparent electrode 23 (equivalent to the first transparent conducting layer in the present invention) arranged on a surface of the sealing glass 28b facing the photosensitive area of the solid imaging device body 29 (see the description of Fig. 12). Claim 3 refers to claim 1, Izuha and Qin disclose the features of claim 1, wherein the packaging component comprises: a cavity arranged on the side of the first transparent substrate facing the photosensitive area of the sensor chip (see fig 19 of qin disclosing cavity); a redistribution layer arranged on a surface of the cavity facing away from the first transparent substrate (see 106 metal titanium layer); a barrier solder mask, wherein at least a part of the barrier solder mask is arranged on the surface of the cavity facing away from the first transparent substrate (see part of 106 covers the substrate, fig 19), an orthographic projection of the barrier solder mask on the first transparent substrate surrounds the orthographic projection of the photosensitive area on the first transparent substrate (see fig 19, disclosing opening in 106 corresponds to light elements), and a thickness of the part of the barrier solder mask arranged on the surface of the cavity facing away from the first transparent substrate is greater than a thickness of the redistribution layer in a direction perpendicular to the first transparent substrate (see structure where 106 sits is of different thicknesses); and a solder mask face arranged on the side of the first transparent substrate facing the photosensitive area of the sensor chip and covering at least a part of the redistribution layer, wherein the solder mask face comprises a plurality of first through holes (see overlapping area of 106 and photo chip). Regarding claim 4, Izuha and Qin disclose the features of claim 3, and Izuha further discloses (see paragraphs 117-159 of the specification, Figure 12): The dimming lamination film 27 further comprises a first transparent electrode 22 insulated from the first conducting layer (equivalent to the second conducting layer in the present invention), the first transparent electrode 22 being arranged on the side of the first conducting layer facing away from the sealing glass 28b, a second transparent conductive layer insulated from the first transparent conductive layer, the second transparent conductive layer is arranged on a side of the first conductive layer facing away from the first transparent substrate (see qin, 116 and 105 are transparent), the cavity comprises a first cavity part and a second cavity part, and the first cavity part is arranged on a surface of the first transparent conductive layer facing away from the first transparent substrate, the second cavity part is arranged on a surface of the second transparent conductive layer facing away from the first transparent substrate, a surface of the first cavity part facing away from the first transparent substrate is flush with a surface of the second cavity part facing away from the first transparent substrate, the second cavity part comprises at least one second through hole, the redistribution layer is arranged on the surfaces of the first cavity part and the second cavity part facing away from the first transparent substrate (see fig 19 disclosing cavity with identical features), and an orthographic projection of the at least one second through hole on the first transparent substrate is within an orthographic projection of the redistribution layer on the first transparent substrate (see orthographic projection in fig 19). Regarding claim 5, Izuha and Qin disclose the features of claim 4, Qin further discloses an electrical connection part arranged in the second through hole and electrically connecting the second transparent conductive layer and the redistribution layer, see 112. The arrangement of the electrical connections will be apparent to a person skilled in the art, and the specific arrangement positions thereof will also be readily conceivable to a person skilled in the art. Regarding claim 6, Izuha and Qin disclose the features of claim 5, and Qin further disclose a material of the electrical connection part is the same as a material of the redistribution layer (see qin disclosing 112, 107 and ). For additional technical features thereof, providing the material of the electrical connections to be the same as the material of the rewiring layer is also easily conceivable for a person skilled in the art. Regarding claim 7, Izuha and Qin disclose the features of claim 3, and further discloses wherein the solder mask face comprises a first mask part and a second mask part, wherein the first mask part is arranged on the surface of the first transparent conductive layer facing away from the first transparent substrate, and the second mask part is arranged on a surface of the cavity or the redistribution layer facing away from the first transparent substrate (see fig 19 disclosing 106, 107 arranged around the cavity), a surface of the first mask part facing away from the first transparent substrate is flush with a surface of the second mask part facing away from the first transparent substrate, and the first mask part comprises at least one third through hole(see fig 19 and 16 disclosing at least four through holes), and an orthographic projection of the at least one third through hole on the first transparent substrate is within an orthographic projection of the first transparent conductive layer on the first transparent substrate (see fig 19 disclosing projection ). Regarding claim 8, Izuha and Qin discloses, for additional technical features thereof, the dimming component is arranged on a side of the first transparent substrate facing away from the packaging component (see fig 19 disclosing substrate and package arranged opposite each other) arranging the dimming assembly on a side of the first transparent substrate facing away from the encapsulation assembly is also a routine option in the art. Regarding claim 9, Izuha and Qin discloses the dimming component comprises a first transparent conductive layer arranged on a surface of the first transparent substrate facing away from the photosensitive area of the sensor chip (see fig 19 disclosing arrangement of light detecting chip facing away from substrate with cavity in between). Regarding claim 10, Izuha and Qin discloses the features found in claim 8, for additional technical features thereof, wherein the dimming component further comprises a second transparent substrate, and the second transparent substrate and the first transparent substrate are bonded and fixed by an optical transparent adhesive, and the first transparent conductive layer is arranged on a surface of the second transparent substrate facing away from the first transparent substrate(see fig 19 disclosing arrangement of light detecting chip facing away from substrate with cavity in between) the specific arrangement of the dimming assembly is also readily conceivable by the skilled person on the basis of the disclosure of Izuha. Regarding claim 22, Izuha and Qin disclose at camera compact module, comprising the image sensor according to claim 1, and a lens module on a light incident side of the image sensor (see Izuha fig 2 disclosing lens 19). Regarding claim 23, Izuha and Qin disclose an electronic device comprising the camera compact module according to claim 22, see para [0094] disclosing camera. Claims 11- 15 are rejected under 35 U.S.C. §103 as being unpatentable over Qin and Izuha and further in view of Xue (CN 209858885 U). Regarding claim 11, Qin and Izuha disclose claim 2, and Xue further discloses the arrangement of the layers of the dimming assembly is also readily conceivable to a person skilled in the art on the basis of the disclosure of Comparative Document 1. For example, Xue discloses an electrochromic layer arranged on a surface of the first transparent conductive layer facing away from the first transparent substrate (see element 20 in fig 2); an ion conductive layer arranged on a surface of the electrochromic layer facing away from the first transparent substrate(see element 20 in fig 2); an ion storage layer arranged on a surface of the ion conductive layer facing away from the first transparent substrate(see element 20 in fig 2, 202/201); and a second transparent conductive layer arranged on a surface of the ion storage layer facing away from the first transparent substrate(see element 20 in fig 2, see 202/201), wherein orthographic projections of the electrochromic layer, the ion conductive layer, the ion storage layer and the second transparent conductive layer on the first transparent substrate are within an orthographic projection of the first transparent conductive layer on the first transparent substrate (see Qin and Izuha as it applies to claim 1). Izuha, Qin and Xue are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Izuha, Qin and Xue. Izuha, Qin and Xue may be combined by forming the dimming layer of Xue in accordance with Izuha and Qin. One having ordinary skill in the art would be motivated to combine Izuha, Qin and Xue in order to form a compact light detector, as variations in dimming layers are known in the art, as taught by Xue. Regarding claim 12, Izuha and Qin discloses the features of claim 1 and Xue further discloses wherein the dimming component comprises a liquid crystal layer sandwiched between a third transparent substrate and a fourth transparent substrate, see 204, figs 1 and 2. Izuha, Qin and Xue are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Izuha, Qin and Xue. Izuha, Qin and Xue may be combined by forming the dimming layer of Xue in accordance with Izuha and Qin. One having ordinary skill in the art would be motivated to combine Izuha, Qin and Xue in order to form a compact light detector, as variations in dimming layers are known in the art, as taught by Xue. Regarding claim 13, Izuha, Qin and Xue discloses the features of claim 12 and further discloses a third transparent conductive layer arranged on a surface of the third transparent substrate facing the liquid crystal layer (see 20/204); a first orientation layer arranged on a surface of the third transparent conductive layer facing the liquid crystal layer (see 201, 203 and 205 disclosing orientation material); a first polarizer arranged on a surface of the third transparent substrate facing away from the liquid crystal layer (see 200 on 204); a fourth transparent conductive layer arranged on a surface of the fourth transparent substrate facing the liquid crystal layer (see 201, 202, 206); a second orientation layer arranged on the surface of the fourth transparent conductive layer facing the liquid crystal layer; and a second polarizer arranged on a surface of the fourth transparent substrate facing away from the liquid crystal layer (see fig 2disclosing 20, and multiple layers of 20), wherein a surface of the first polarizer facing away from the third transparent substrate and a surface of the first transparent substrate facing away from the packaging component are bonded and fixed by an optical transparent adhesive (see figs 1-3 disclosing this arrangement). Regarding claim 14, Izuha, Qin and Xue disclose the image sensor according to claim 12, wherein the third transparent substrate and the fourth transparent substrate are thin glass substrates (see Xue disclosing 201 to be glass). Regarding claim 15, Izuha, Qin and Xue disclose the image sensor according to claim 12, wherein the third transparent substrate and the fourth transparent substrate are flexible substrates (see Xue disclosing flexible polymer material). Claim 16, 17, and 19 are rejected under 35 U.S.C. 103§ as being unpatentable over Izuha, Qin and Xue as applied to claim 12 and further in view of Zhang (CN 114675519 A). Regarding claim 16, Izuha ,Qin and Xue disclose the image sensor according to claim 12, wherein the dimming component further comprises: a first nano-grating array arranged on a surface of the third transparent substrate facing the liquid crystal layer (see Xue disclosing polarization), and Zhang discloses the first nano-grating array comprising a plurality of nanowires extending in a first direction; and a second nano-grating array arranged on a surface of the fourth transparent substrate facing the liquid crystal layer, the second nano-grating array comprising a plurality of nanowires extending in a second direction, wherein the first direction is perpendicular to the second direction (see Zhang discloses nanowires polarization, see claim 10). Izuha, Qin, Xue and Zhang are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Izuha, Qin, Xue and Zhang. Izuha, Qin and Xue may be combined by forming the dimming layer of Xue and Zhang in accordance with Izuha and Qin. One having ordinary skill in the art would be motivated to combine Izuha, Qin and Xue and in order to form a compact light detector, as variations in dimming layers are known in the art, as taught by Zhang . Regarding claim 17, Izuha, Qin, Xue and Zhang disclose the image sensor according to claim 16, wherein the dimming component further comprises: a fifth transparent conductive layer arranged a surface of the third transparent substrate facing the liquid crystal layer and filling gaps between a plurality of nanowires of the first nano- grating array; a third orientation layer arranged on a surface of the fifth transparent conductive layer facing the liquid crystal layer; a sixth transparent conductive layer arranged on a surface of the fourth transparent substrate facing the liquid crystal layer and filling gaps between a plurality of nanowires of the second nano- grating array; and a fourth orientation layer arranged on a surface of the sixth transparent conductive layer facing the liquid crystal layer (see figs 1-2 discloses multiple layers). It would have been obvious to form multiple dimming layers, as known in the art. Regarding claim 19, Izuha, Qin, Xue and Zhang disclose the image sensor according to claim 16, wherein the third transparent substrate and the first transparent substrate are the same transparent substrate (see figs 1-2 of Xue disclosing transparent layers and substrate). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDWARD CHIN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 16, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+6.8%)
2y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 692 resolved cases by this examiner. Grant probability derived from career allowance rate.

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