Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Preliminary Amendment, received 5/17/2024, has been entered.
Claims 1-25 are presented for examination.
Specification
The abstract of the disclosure is objected to because the reference numbers corresponding to the drawings. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guan et al. (US Pub. No. 2021/0210481 A1), hereafter referred to as Guan.
As to claim 1, Guan discloses a semiconductor device (fig 2 [0026]), comprising:
a substrate (202);
a first nitride semiconductor layer (204; [0022], [0026]) on the substrate (202);
a second nitride semiconductor layer (206; [0022], [0026]) on the first nitride semiconductor layer (204);
a switching element (220) on the second nitride semiconductor layer (206);
a capacitor (C) adjacent to the switching element (220); and
a clamping element (M5-Mn and R) on the second nitride semiconductor layer (206), wherein the clamping element (M5-Mn and R) is adjacent to the capacitor (C) and electrically connected to the switching element (220).
As to claim 2, Guan discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the second nitride semiconductor layer has a band gap larger than a band gap of the first semiconductor layer ([0022]).
As to claim 5, Guan discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the switching element comprises a diode ([0040]).
As to claim 16, Guan discloses a method for manufacturing a semiconductor device (fig 2 [0026]), comprising:
forming a first nitride semiconductor layer (204) on a substrate (202);
forming a second nitride semiconductor layer (206) on the first nitride semiconductor layer (204);
forming a switching element (220) on the second nitride semiconductor layer (206);
forming a capacitor (C) adjacent to the switching element (220); and
forming a clamping element (M5-Mn and R) on the second nitride semiconductor layer (206), wherein the clamping element (M5-Mn and R) is adjacent to the capacitor (C) and electrically connected to the switching element (220).
As to claim 19, Guan discloses the method according to claim 16 (paragraphs above),
forming a transistor (MHEMT) adjacent to and electrically connected to the switching element (220), wherein the transistor (MHEMT) comprises a source electrode (S), a gate electrode (G) and a drain electrode (D) which are formed on the second nitride semiconductor layer (206).
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Udrea et al. (US Pub. No. 2020/0168599 A1), hereafter referred to as Udrea.
As to claim 21, Udrea discloses a semiconductor device (figs 20a-c; [0146]), comprising:
a substrate (substrate 4);
a first nitride semiconductor layer (GaN layer 2) on the substrate (4);
a second nitride semiconductor layer (AlGaN layer 1) on the first nitride semiconductor layer (2) and having a band gap greater than a band gap of the first semiconductor layer (AlGaN has a greater band gap than GaN);
a transistor (10) on the second nitride semiconductor layer (1); and
a protection circuit (aux transistor and diode 31) on the second nitride semiconductor layer (1), wherein the protection circuit is configured to dispel electrons from a gate node (10) of the transistor when a voltage on the gate node exceeds a first threshold voltage ([0146]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4, 6-15, 17-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guan in view of Udrea.
As to claim 3, Guan discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the switching element (220) comprises a first conductive structure (gate) on the second nitride semiconductor layer (206), electrically connected to the capacitor (C) and the clamping element (drain of Mn) through a first conductive layer (conductor through 210) and a second conductive layer (conductor through 208).
Guan does not explicitly disclose that the conductors/interconnects are metal layers.
Nonetheless, Udrea discloses a similar circuit structure wherein conductive layers are metal layers ([0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the conductive interconnect layers of Guan as metal layers as taught by Udrea since this will create a low resistance electrical connection.
As to claim 4, Guan in view of Udrea disclose the semiconductor device according to claim 3 (paragraphs above).
wherein the switching element (220) further comprises:
a second conductive structure (conductive layer through 208 connected to drain D) on the second nitride semiconductor layer (206); and
a third conductive structure (conductive layer through 208 connected to source S) on the second nitride semiconductor layer (206), wherein the second conductive structure and the third conductive structure are electrically connected to the clamping element (M5) through a third interconnect layer (interconnect through layer 210 connected to D) and a fourth interconnect layer (interconnect through layer 210 connected to S).
Guan does not explicitly disclose that the conductors/interconnects are metal layers.
Nonetheless, Udrea discloses a similar circuit structure wherein conductive layers are metal layers ([0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the conductive interconnect layers of Guan as metal layers as taught by Udrea since this will create a low resistance electrical connection.
As to claim 6, Guan in view of Udrea disclose the semiconductor device according to claim 4 (paragraphs above),
Guan further discloses a transistor (MHEMT) electrically connected to the switching element (220), wherein the transistor (MHEMT) comprises a source electrode (S), a gate electrode (G) and a drain electrode (D) which are disposed on the second nitride semiconductor layer (206).
As to claim 7, Guan in view of Udrea disclose the semiconductor device according to claim 6 (paragraphs above),
Guan further discloses wherein the gate electrode (G) of the transistor (MHEMT) is electrically connected to the switching element (220) and the clamping element (M5) through the third conductive layer (conductive layer through 206) and the fourth conductive layer (conductive layer through 210).
As to claim 8, Guan in view of Udrea disclose the semiconductor device according to claim 3 (paragraphs above),
Guan further discloses wherein the capacitor (C) comprises:
a fifth conductor layer (lower conductor) on the second nitride semiconductor layer (206);
a conductive layer (upper conductor); and
an insulating layer between the fifth metal layer and the conductive layer ([0030]).
As to claim 9, Guan in view of Udrea disclose the semiconductor device according to claim 8 (paragraphs above),
Guan further discloses wherein an area of the conductive layer is substantially equal to an area of the insulating layer (the insulating layer between the Cbottom and Ctop is considered to be the area of the layer), and the area of the conductive layer is smaller than an area of the fifth metal layer (upper capacitor layer is less than bottom as shown in figure 2).
As to claim 10, Guan in view of Udrea disclose the semiconductor device according to claim 8 (paragraphs above),
Guan further discloses wherein the clamping element (Mn) comprises a fourth conductive structure (interconnection) on the second nitride semiconductor layer (206), electrically connected to the fifth metal layer of the capacitor (interconnect for capacitor C).
As to claim 11, Guan in view of Udrea disclose the semiconductor device according to claim 10 (paragraphs above),
Guan further discloses wherein the clamping element (Mn-3) further comprises a fifth conductive structure (interconnect) on the second nitride semiconductor layer (206), electrically connected to the first metal layer through a sixth metal layer (interconnections through dielectrics 208 and 210).
As to claim 12, Guan in view of Udrea disclose the semiconductor device according to claim 11 (paragraphs above),
Guan further discloses wherein the clamping element (M5) further comprises a sixth conductive structure (interconnect) on the second nitride semiconductor layer (206), electrically connected to the third metal layer through a seventh metal layer (interconnections through dielectric 208 and 210).
As to claim 13, Guan in view of Udrea disclose the semiconductor device according to claim 12 (paragraphs above),
Guan further discloses wherein the first metal layer and the third metal layer are located substantially in a first plane (interconnect layers in dielectric 208).
As to claim 14, Guan in view of Udrea disclose the semiconductor device according to claim 13 (paragraphs above),
Guan further discloses wherein the second metal layer, the fourth metal layer, the fifth metal layer, the sixth metal layer and the seventh metal layer are located substantially in a second plane (interconnect layer in dielectric 210), and the second plane is substantially parallel with the first plane (planes of dielectrics 208 and 210 are parallel with each other).
As to claim 15, Guan in view of Udrea disclose the semiconductor device according to claim 14 (paragraphs above),
Guan further discloses wherein the insulating layer and the conductive layer of the capacitor is between the first plane and the second plane (Capacitor C comprising Cbottom and Ctop between first and second parallel planes).
As to claim 17, Guan discloses the method according to claim 16 (paragraphs above),
wherein forming the switching element (220) further comprises forming a first conductive structure (interconnect through dielectric 208) on the second nitride semiconductor layer (206), electrically connected to the capacitor (C) and the clamping element (M5) through a first interconnect layer and a second interconnect layer (interconnect layers through 210).
Guan does not explicitly disclose that the conductors/interconnects are metal layers.
Nonetheless, Udrea discloses a similar circuit structure wherein conductive layers are metal layers ([0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the conductive interconnect layers of Guan as metal layers as taught by Udrea since this will create a low resistance electrical connection.
As to claim 18, Guan in view of Udrea disclose the method according to claim 17 (paragraphs above).
Guan further discloses wherein forming the switching element (220) further comprises:
forming a second conductive structure (interconnect structure) on the second nitride semiconductor layer (206); and
forming a third conductive structure on the second nitride semiconductor layer (interconnect structure on 206), wherein the second conductive structure and the third conductive structure are electrically connected to the clamping element (M5) through a third interconnect layer and a fourth interconnect layer (interconnect layers through 208 and 210).
Guan does not explicitly disclose that the conductors/interconnects are metal layers.
Nonetheless, Udrea discloses a similar circuit structure wherein conductive layers are metal layers ([0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the conductive interconnect layers of Guan as metal layers as taught by Udrea since this will create a low resistance electrical connection.
As to claim 20, Guan discloses the method according to claim 16 (paragraphs above),
Guan further discloses wherein forming the capacitor (C) further comprises:
forming a fifth conductor layer (Cbottom);
forming an insulating layer (capacitor insulator layer) formed on the fifth conductor layer (Cbottom); and
forming a conductive layer (Ctop) formed on the insulating layer (capacitor insulator layer).
Guan does not explicitly disclose that the conductors/interconnects are metal layers.
Nonetheless, Udrea discloses a similar circuit structure wherein conductive layers are metal layers ([0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the conductive interconnect layers of Guan as metal layers as taught by Udrea since this will create a low resistance electrical connection.
Claim(s) 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Udrea in view of Guan.
As to claim 22, Udrea discloses the semiconductor device according to claim 21 (paragraphs above),
wherein the protection circuit further comprises:
a switching element (diode 31) on the second nitride semiconductor layer (1); and
a clamping element (aux transistor) on the second nitride semiconductor layer (1), wherein the clamping element (aux transistor) is electrically connected to the switching element (31).
Udrea does not disclose a capacitor adjacent to the switching element and the clamping element is adjacent to the capacitor.
Nonetheless, Guan discloses a similar HEMT power circuit on a nitride semiconductor layer that further includes a capacitor (fig 3, C) adjacent to a HEMT transistor (M).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to further include the voltage detection circuit comprising the capacitor and a switching circuit of Guan into the circuit of and included on the second nitride semiconductor of Udrea since this will prevent the voltage of the drain from being too high.
As to claim 23, Udrea in view of Guan disclose the semiconductor device according to claim 22 (paragraphs above).
Udrea further discloses wherein the switching element (31) comprises:
a first conductive structure (16) on the second nitride semiconductor layer (1), the clamping element (aux transistor) through a first metal layer and a second metal layer (metal interconnects 16 and 15);
a second conductive structure (10) on the second nitride semiconductor layer (1); and
a third conductive structure (adjacent portion of 16) on the second nitride semiconductor layer (1), wherein the second conductive structure and the third conductive structure are electrically connected to the clamping element (Aux transistor) through a third metal layer and a fourth metal layer (layers 15 and 16).
As to claim 24, Udrea in view of Guan disclose the semiconductor device according to claim 22 (paragraphs above).
Guan further discloses wherein the capacitor (C) comprises:
a fifth metal layer (Cbottom) on the second nitride semiconductor layer (206);
a conductive layer (Ctop); and
an insulating layer (capacitor dielectric) between the fifth metal layer (Cbottom) and the conductive layer (Ctop).
As to claim 25, Udrea in view of Guan disclose the semiconductor device according to claim 24 (paragraphs above).
Guan further discloses wherein an area of the conductive layer (Ctop) is substantially equal to an area of the insulating layer (capacitor dielectric between Ctop and Cbottom), and the area of the conductive layer (Ctop) is smaller than an area of the fifth metal layer (Cbottom).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2025/0132757A1; US 2023/0335464A1; and US 20210335781A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/13/2026
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