CTNF 18/711,187 CTNF 90253 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application. The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office. Priority 2. Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 08/07/2024 is being considered by the Examiner. Disposition of the Claims 4. The instant application was effectively filed on November 30, 2021, wherein claims 1-8 were previously canceled and claims 9-14 are pending. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-fti The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-fti The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-fti Claim s 9, 11-14 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ikeda et al. US PG-PUB 20210295780 A1 (hereinafter Ikeda) in view of Ikeda US PG-PUB 20170208254 A1 (hereinafter Ikeda254) and further in view of Kusunoki et al. US PG-PUB 20210103419 A1 (hereinafter Kusunoki) . PNG media_image1.png 677 672 media_image1.png Greyscale Regarding claim 9 , Ikeda teaches A display apparatus ( Fig’s 1-3; a display device 10 ) comprising: a first layer over a substrate ( Fig’s 1-3; a layer 20 ), the first layer comprising a first driver circuit and a second driver circuit ( Fig’s 1-3 and Para. [0078]; layer 20 includes a gate driver circuit 21, a source driver circuit 22 ); and a second layer over the first layer ( Fig’s 1-3; layer 30 over layer 20 ), the second layer comprising a first display region and a second display region ( See Fig’s 2-3; display portion 33 ), wherein the first display region comprises a first pixel ( Fig. 3; the pixel 34 ), wherein the second display region comprises a second pixel ( Fig. 1-3; the pixel 34 ), wherein the first pixel comprises a first light-emitting diode ( Fig.’s 1-3 and Para. [0083] and Para. [0161]-[0163]; light with luminance corresponding to the image signals is emitted from the pixels 34, whereby an image is displayed on the display portion 33 ), wherein the second pixel comprises a second light-emitting diode ( Fig.’s 1-3 and Para. [0083] and Para. [0161]-[0163]; light with luminance corresponding to the image signals is emitted from the pixels 34 ), wherein each of the first pixel and the second pixel comprises a transistor comprising a metal oxide in a channel formation region ( Para. [0014]; the pixel may include a transistor including a metal oxide in a channel formation region, and the metal oxide may include an element M (M is Al, Ga, Y, or S ), although Ikeda further teaches as disclosed in Para. [0104]; In the display device 10 having the structure illustrated in FIG. 6, the gate driver circuit 21a can operate to write image signals to all the pixels 34 in the odd-numbered rows, and then the gate driver circuit 21b can operate to write image signals to all the pixels 34 in the even-numbered rows. That is, the display device 10 having the structure illustrated in FIG. 6 can operate by an interlace method. With an interlace method, the operating speed of the display device 10 can be increased and the frame frequency can be increased. In addition, the number of pixels 34 to which image signals are written in one frame period can be half that when the display device 10 operates by a progressive method. Thus, in the display device 10, the clock frequency can be lower in interlace driving than in progressive driving; hence, power consumption of the display device 10 can be reduced. Ikeda fails to explicitly disclose wherein each of the first driver circuit and the second driver circuit comprises a first transistor comprising silicon in a channel formation region, wherein the first display region is configured to display an image with a first frame frequency, wherein the second display region is configured to display an image with a second frame frequency, and wherein the first frame frequency is different from the second frame frequency. However, in the same of endeavor, Ikeda254 teaches wherein each of the first driver circuit and the second driver circuit comprises a first transistor comprising silicon in a channel formation region ( Para. [0014] and Para. [0185]; The driver circuit can include a second transistor including silicon in an active layer or an active region ), Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ikeda with the teachings as taught by Ikeda254 in order to control overall frequency Ikeda254 -( Para. [0142] ). Furthermore, the disclosure of Ikeda as modified by Ikeda254 fails to further explicitly disclose wherein the first display region is configured to display an image with a first frame frequency, wherein the second display region is configured to display an image with a second frame frequency, and wherein the first frame frequency is different from the second frame frequency. However, in the same of endeavor, Kusunoki teaches wherein the first display region is configured to display an image with a first frame frequency, wherein the second display region is configured to display an image with a second frame frequency, and wherein the first frame frequency is different from the second frame frequency ( Para. [0018] In the above, a first image on the first display portion is preferably displayed at a lower frame frequency than a second image on the second display portion ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ikeda as modified by Ikeda254 with the teachings as taught by Kusunoki, in order to reduce the power consumption due to controlling of the frequency Kusunoki -( Para. [0056] ). Regarding claim 11 , Ikeda as modified by Ikeda254 and Kusunoki teaches The display apparatus according to claim 9, Ikeda254 further teaches wherein the substrate comprises a glass substrate ( Para’s. [0275] and [0395]; glass substrate ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ikeda as modified by Ikeda254 and Kusunoki, in to improve to display quality of the display device. Regarding claim 12 , Ikeda as modified by Ikeda254 and Kusunoki teaches The display apparatus according to claim 9, Kusunoki further teaches wherein the first transistor comprises polysilicon in the channel formation region ( Para. [0095] ). Regarding claim 13 , Ikeda as modified by Ikeda254 and Kusunoki teaches The display apparatus according to claim 9, Ikeda further teaches wherein the first driver circuit and the first pixel overlap each other, and wherein the second driver circuit and the second pixel overlap each other ( Fig’s. 1-4 layer 20 which comprises gate driver circuit 21, a source driver circuit 22 overlaps pixel 34 ). Regarding claim 14 , Ikeda as modified by Ikeda254 and Kusunoki teaches The display apparatus according to claim 9, further comprising a wiring between the first layer and the second layer ( Fig’s. 1 and 5; i.e. wiring 31 and/or 32 ), wherein the wiring is electrically connected to the first pixel and the first driver circuit ( Fig’s. 1 and 5; wiring 31 ), and wherein the wiring extends in a direction perpendicular to or a direction substantially perpendicular to the substrate ( see Fig’s. 1 and 5 ) . 07-21-fti Claim 10 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Ikeda et al. US PG-PUB 20210295780 A1 (hereinafter Ikeda) in view of Ikeda US PG-PUB 20170208254 A1 (hereinafter Ikeda254) and Kusunoki et al. US PG-PUB 20210103419 A1 (hereinafter Kusunoki) and further in view of Hong et al. US PG-PUB 20190012029 A1 (hereinafter Hong) . Regarding claim 10 , Ikeda as modified by Ikeda254 and Kusunoki teaches The display apparatus according to claim 9, although the disclosure of Ikeda as modified by Ikeda254 and Kusunoki teaches having a touch sensor for i.e. see Kusunoki Para. [0043]-[0044]; a display panel (or a display device) with a touch sensor or a display panel (or a display device) having a touch sensor function. Ikeda as modified by Ikeda254 and Kusunoki fails to further disclose wherein the first display region further comprises a first sensor portion, wherein the second display region further comprises a second sensor portion, wherein the first sensor portion is positioned over the first light-emitting diode, and wherein the second sensor portion is positioned over the second light-emitting diode. However, in the same field of touch display, Hong teaches wherein the first display region further comprises a first sensor portion ( See Fig’s. 1-2; DA1 ), wherein the second display region further comprises a second sensor portion ( Fig.’s 1-2; DA2 ), wherein the first sensor portion is positioned over the first light-emitting diode, and wherein the second sensor portion is positioned over the second light-emitting diode ( Fig.’s 1-2 and 4; the sensor Tp is positioned over light emitting diode Dp which comprises light emitting elements 120 ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ikeda as modified by Ikeda254 and Kusunoki with the teachings as taught by Hong, in order a desired input in response to the viewing image can be conveniently provided. Conclusion 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY ONYEKABA whose telephone number is (571)270-7633. The examiner can normally be reached on 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, NITIN K PATEL can be reached on 5712727677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMY ONYEKABA/Primary Examiner, Art Unit 2628 Application/Control Number: 18/711,187 Page 2 Art Unit: 2628 Application/Control Number: 18/711,187 Page 3 Art Unit: 2628 Application/Control Number: 18/711,187 Page 4 Art Unit: 2628
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