Prosecution Insights
Last updated: October 02, 2026
Application No. 18/711,620

LIGHT-EMITTING DIODE ELEMENT

Non-Final OA §102§103§112
Filed
May 20, 2024
Priority
Nov 24, 2021 — JP 2021-189929 +2 more
Examiner
CHAN, CANDICE
Art Unit
Tech Center
Assignee
Stanley Electric Co., Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
403 granted / 555 resolved
+12.6% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
615
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 555 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the application filed 20 May 2024. Claims 1-9 are currently pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation “and has a layer thickness” at line 3; it is unclear which previously recited layer this limitation is intended to refer to, i.e., the active layer or the spacer layer. For the purposes of examination, it is assumed the above limitation refers to the thickness of the active layer. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 108511572 A to Liang et al. (citations refer to the English machine translation attached; hereinafter “Liang”). Regarding independent claim 1, Liang (Fig. 1) discloses a light-emitting diode element comprising: a substrate 101 (p. 3, Description para. 2) with a moth-eye nano pattern on a surface of the substrate in which cone-shaped protrusions are periodically formed (Fig. 1; para. bridging p. 2-3); a first semiconductor layer 102 (p. 3, Description para. 2) configured to be formed on the moth-eye nano pattern and have a photonic crystal layer 103 (p. 3, Description para. 2); an active layer 106 (p. 3, Description para. 2) configured to be formed on the first semiconductor layer 102 and have a light-emitting layer (para. bridging p. 3-4; Fig. 1); and a second semiconductor layer 107 (p. 3, Description para. 2) configured to be formed on the active layer (Fig. 1). Regarding claim 3, Liang (Fig. 1) discloses the light-emitting diode element according to claim 1, wherein a first low refractive index layer 103 and a second low refractive index layer 107 having an effective refractive index lower than the active layer are formed with the active layer 106 sandwiched therebetween, and the photonic crystal layer 103 is the first low refractive index layer 103 (p. 3, Description para. 2; p. 4, first full para. – MQW material of 106 having higher refractive index than that of the materials of 103 and 107). Regarding claim 9, Liang (Fig. 1) discloses the light-emitting diode element according to claim 1; the limitations “a center position of the light-emitting layer coincides with a peak position of a light intensity distribution of the TE0 mode light of the active layer” are considered claimed properties or functions. Liang discloses the structure as recited in the claim as currently drafted, thus the structure of Liang is presumed to possess the claimed properties or functions of the claimed structure. MPEP § 2112.01(I). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liang as applied to claim 1 above, and further in view of JP 2020-107778 A to Kashima et al. (citations refer to the English machine translation attached; hereinafter “Kashima”). Regarding claim 2, Liang discloses the light-emitting diode element according to claim 1, however fails to expressly disclose: wherein when a lattice constant of the photonic crystal layer is a, a refractive index of a material of the first semiconductor layer is neff, and an arbitrary wavelength (in a vacuum) within a full width at half maximum of an emission spectrum of the light-emitting layer is λw, the photonic crystal layer has only photonic crystals satisfying a square lattice arrangement and a ≠ mλw/neff (m is a natural number), or the photonic crystal layer has only photonic crystals satisfying a triangular lattice arrangement and a ≠ mλw × 2/(3/2 × neff) (m is a natural number). In the same field of endeavor, Kashima (Fig. 1C) discloses a light-emitting diode element including a photonic crystal layer with a crystal periodic structure arranged in a triangular lattice shape and wherein a ≠ mλw × 2/(3/2 × neff) (see Kashima at Fig. 1C; p. 3, last para. – p. 4, first para. - disclosing photonic crystal structure satisfying the Bragg conditional expression mλ/neff = 2a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a triangular lattice shape as taught by Kashima in the element of Liang for the purpose of increasing light extraction efficiency. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liang as applied to claim 1 above, and further in view of US 2019/0369294 A1 to Chang et al. (hereinafter “Chang”). Regarding claim 4, Liang discloses the light-emitting diode element according to claim 1, however fails to expressly disclose: wherein when the protrusions of the moth-eye nano pattern are arranged in a lattice, a period of the protrusions is P, an emission wavelength of the light-emitting layer is λ, and a refractive index of a medium on a light-emitting layer side of the moth-eye nano pattern is ns, P < λ/ns is satisfied. In the same field of endeavor, Chang discloses protrusions of a moth-eye nano pattern arranged in a lattice (¶ 0028), a period of the protrusions is P (¶ 0028 – 250nm), an emission wavelength of the light-emitting layer is λ (¶ 0028 – 633nm), and a refractive index of a medium on a light-emitting layer side of the moth-eye nano pattern is ns (¶ 0028 – 1.7 or 1.45), P < λ/ns is satisfied (250 < 633/(1.7 or 1.45). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the relationship as taught by Chang in the element of Liang for the purpose of minimizing interfacial reflection (Chang, ¶ 0024). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liang. Regarding claim 5, Liang discloses the light-emitting diode element according to claim 1, wherein when air holes in the photonic crystal layer 103 have a cylindrical shape (p. 4, first full para.), the air holes are arranged at square lattice point positions (p. 4, first full para.), a lattice constant of the air holes is a (p. 2, third para. from bottom – 100-1000nm). Liang fails to expressly disclose: a diameter of the air holes is d, and 0.3 ≤ d/a is satisfied. However, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the lattice constant (period) of the air holes and the diameter of the air holes, such that they coincide with the recited relationship, for the purpose of optimizing the reflection characteristics of the photonic crystal layer in order to increase the light extraction efficiency of the light-emitting diode element. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liang as applied to claim 5 above, and further in view of US 2017/0358712 A1 to Kashima et al. (hereinafter “Kashima ‘712”). Regarding claim 6, Liang discloses the light-emitting diode element according to claim 5, wherein the first semiconductor layer 102 is made of GaN (p. 4, first para.). Liang fails to expressly disclose: a depth of the air holes of the photonic crystal layer is equal to or more than a penetration depth of evanescent light in TE0 mode light from the light-emitting layer. In the same field of endeavor, Kashima ‘712 discloses a method of optimizing the configuration of airholes 101h (¶ 0068) of a photonic crystal layer (¶¶ 0068, 0070-76), noting that TE light incident on the airholes is reflected (¶ 0070). Thus, in view of the teachings of Kashima, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide airholes having a depth equal to or more than a penetration depth of evanescent light in TE0 mode light from a light-emitting layer for the purpose of ensuring reflection of the light and increasing light extraction efficiency of the light-emitting diode element (¶ 0076). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liang as applied to claim 1 above, and further in view of JP 2014-149323 to Hasegawa (citations refer to the English machine translation attached herewith; hereinafter “Hasegawa”). Regarding claim 7, as best understood, Liang discloses the light-emitting diode element according to claim 1, however fails to expressly disclose: wherein the active layer includes a spacer layer formed on the light-emitting layer, and has a layer thickness such that only TE0 to TE5 mode light is guided. In the same field of endeavor, Hasegawa discloses a light-emitting element including an active layer (including MQW structure) which includes a spacer layer (waveguide) formed on the light-emitting layer (p.2, para. 2), wherein the layer thickness, layer strain, and width are variables optimized for optical amplification and the output of polarized light according to design requirements (p. 2, para. 2). In view of the teachings of Hasegawa, it would have been obvious to and within the skill of one of ordinary skill in the art before the effective filing date of the claimed invention to provide the appropriate layer thickness such that only TE0 to TE5 mode light is guided since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the layer thickness is considered a result effective variable because it affects light output. Thus the ordinary artisan would have been motivated to modify the layer thickness for the purpose of producing a light-emitting diode element with desired light output characteristics. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liang as applied to claim 1 above, and further in view of US 2013/0015483 A1 to Shimokawa et al. (hereinafter “Shimokawa”). Regarding claim 8 Liang (Fig. 1) discloses the light-emitting diode element according to claim 1, wherein an LED structural layer including the first semiconductor layer 101, the active layer 106, and the second semiconductor layer 107 has a rectangular parallelepiped shape (Fig. 1). Liang does not expressly disclose: a reflective film covering at least four sides of the light-emitting layer is formed, and wherein when the reflective film is a dielectric multilayer film in which high refractive index films and low refractive index films are alternately stacked, an emission wavelength of the light-emitting layer is λ, an incidence angle of the TE0 mode light is α, a refractive index of the high refractive index film is nh, and a film thickness is dh, the following formula holds: nhdhcosα=λ/4 or nhdhcosα=3λ/4. In the same field of endeavor, Shimokawa (Fig. 1B) discloses a light-emitting diode element including a reflective film 61 (¶ 0097) covering at least four sides of the light-emitting layer 30 (¶ 0031) and wherein when the reflective film is a dielectric multilayer film in which high refractive index films and low refractive index films are alternately stacked (¶ 0097), an emission wavelength of the light-emitting layer is λ, an incidence angle of the TE0 mode light is α, a refractive index of the high refractive index film is nh (variables represent values inherent to the particular materials utilized). Shimokawa discloses providing layer thicknesses of the dielectric multilayer film according to the wavelengths of light desired to be reflected, to optimize for efficient reflection (¶ 0097), however does not expressly disclose providing a film thickness dh by which the recited formula holds: nhdhcosα=λ/4 or nhdhcosα=3λ/4. In view of the teachings of Shimokawa, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the claimed film thickness dh consistent with the recited formula relationships, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the film thickness is considered a result effective variable because it affects the reflectivity of the reflective film. Thus the ordinary artisan would have been motivated to modify the film thickness for the purpose of efficient reflection of light. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 19 September 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

May 20, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12666994
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 0m to grant Granted Jun 23, 2026
Patent 12660678
EMBEDDED PACKAGE WITH DELAMINATION MITIGATION
4y 9m to grant Granted Jun 16, 2026
Patent 12660641
SEMICONDUCTOR DEVICES HAVING WETTABLE FLANKS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 9m to grant Granted Jun 16, 2026
Patent 12641780
THREE-DIMENSIONAL FLASH MEMORY DEVICE AND METHOD FOR FORMING THE SAME
3y 4m to grant Granted May 26, 2026
Patent 12635188
SEMICONDUCTOR DEVICE INCLUDING MEMORY STRUCTURE ARRANGED ADJACENT TO PLANAR GATE STRUCTURE
3y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+19.3%)
3y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 555 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month