Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 13, 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jian (CN 112037649 A, from IDS).
Regarding claim 1, Jian discloses a display panel (Fig. 2: 100) having a pixel region (110), a fanout region (122) and a bonding region (121) disposed at a side of the pixel region (Y direction “side”) and sequentially disposed in a direction (Y direction) away from the pixel region;
wherein the display panel comprises a substrate (10), a driver chip (Fig. 8: 20) located on the substrate (“on” in the Z direction) and disposed in the bonding region (pg. 6 of translation: “the binding area 121 for setting the driving chip 20”);
the driver chip comprises a plurality of bonding pads (Fig. 4: 21/22/23);
the display panel further comprises a plurality of fanout traces (Fig. 2: 15) located on the substrate;
an end of each of the fanout traces (“end” at region 121) is connected with a bonding pad (13) and the other end of each of the fanout traces (“end” at region 110) extends to the pixel region through the fanout region (“through” in the Y direction);
a distance (Y distance) between a part of the bonding pads and a first edge of the driver chip (Fig. 4: edge 201) gradually increases along a direction (X direction) parallel to the first edge (“distance” for respective pads as measured in the Y direction “increases” compared to other “pads” compared to each other along the X direction, which is “parallel to the first edge”. Note: this is consistent with Applicant’s disclosure, Fig. 4);
the driver chip has a plurality of support regions (B) disposed on a side (Y side) of the part of the bonding pads close to the fanout region;
the driver chip further comprises redundant pads (11) located in the support regions;
a part of the fanout traces (the part on the right, See annotated figure for direction designation) passes through an area between adjacent support regions (“adjacent” in the X direction);
a part of the fanout traces (the part on the right, See annotated figure for direction designation) passes through the support regions and is disposed to be insulated from the redundant pads (Fig. 13: shows insulation layers (not annotated) on 15 and with pad 11; pg. 12 : “corresponding insulating layer”).
Illustrated below are marked and annotated figures of Fig. 2 and Fig. 4, Fig. 8, and a marked and annotated figure of Fig. 13 of Jian.
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Regarding claim 2, Jian discloses the display panel according to claim 1 (Fig. 13), wherein the redundant pads comprise:
a first insulation layer (See annotated figure), a second insulation layer (See annotated figure), and a first transparent electrode layer (50; pg. 12: “transparent conductive layer”) located on the substrate and sequentially disposed in a direction (Z direction, See annotated figure for direction designation) away from the substrate;
the fanout traces comprise first sub-fanout traces (all traces 15);
the first sub-fanout traces are located on a side of the substrate (the same Z side) close to the first insulation layer (traces 15 are directly contacting the 1st insulation layer, thus they are “close”).
Regarding claim 13, Jian discloses the display panel according to claim 2 (Fig. 13), wherein the first transparent electrode layer coincides with the support regions (“coincides” because Fig. 13 shows this electrode layer within 11, which as previously cited, is a structure within Fig. 2: region B).
Regarding claim 15, Jian discloses the display panel according to claim 2 (Fig. 13), wherein the first insulation layer and the second insulation layer are each connected as an integral structure between the adjacent support regions (each insulation layer is illustrated as a continuous conformal layer, thus, each of these layers are necessarily “connected as an integral structure between the adjacent support regions”).
Regarding claim 16, Jian discloses a display device (Fig. 24), wherein the display device comprises the display panel of claim 1 (pg. 18: “the display device comprises a display panel provided by the embodiment of the present invention”).
Regarding claim 17, Jian discloses the display panel according to claim 2 (Fig. 13), wherein the first insulation layer and the second insulation layer are made of at least one of silicon nitride and silicon oxide (both are disclosed; pg. 12: “the inorganic insulating layer can be SiNx or SiOx”).
Regarding claim 18, Jian discloses the display panel according to claim 2 (Fig. 13), wherein the first transparent electrode layer is made of a transparent conductive material (citation repeated here: 50; pg. 12: “transparent conductive layer”).
Allowable Subject Matter
Claims 3-12 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 3-12 and 19-20 is the inclusion of the limitation “wherein the redundant pads further comprise a first metal layer located on a side of the substrate close to the first insulation layer; the first metal layer comprises a plurality of first metal strips arranged at intervals; the first sub-fanout traces are located between adjacent first metal strips” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first metal strips”, “arranged at intervals”, and “between” in combination with all other limitations in claims 3, 2, and 1. The prior art of record generally teaches these structures but fails to teach the claimed arrangement. Searches elsewhere in the prior art failed to anticipate the claim, and also failed to teach or be reasonably combined with the prior art in a way that would render obvious to specifically claimed arrangement.
The primary reason for the allowable subject matter of claim 14 is the inclusion of the limitation “wherein the first transparent electrode layer is connected as an integral structure between the adjacent support regions” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first transparent electrode layer”, “connected as an integral structure”, and “between” in combination with all other limitations in claims 14, 2, and 1. The prior art of record generally teaches these structures but fails to teach the claimed shape and arrangement. Searches elsewhere in the prior art failed to anticipate the claim, and also failed to teach or be reasonably combined with the prior art in a way that would render obvious to specifically claimed shape and arrangement.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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