DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-19 remain pending in this application. Acknowledgement is made of the amendment received 05/20/2024. Claims 5, 10, 11, 15, 17, and 18 are amended.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al (US 20210272889 A1, hereafter Wu).
Regarding claim 1, Wu discloses: An integrated circuit package structure (Wu 100, fig 1, ¶0014), comprising:
a substrate (Wu 300, ¶0018);
at least two redistribution layers (Wu 200, 500, ¶0018-0019), wherein the at least two redistribution layers are stacked on the substrate (Wu fig 1), and a metal connection line (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032) of a redistribution layer (Wu 200) adjacent to the substrate (Wu fig 1) is connected with a metal connection line of the substrate (Wu 320, 340A, 340B, ¶0042-0044)(Wu fig 1), and metal connection lines of two adjacent redistribution layers are connected to each other (Wu fig 1, ¶0010, 0017-0020);
a die (Wu 600, ¶0014-0015), wherein the die is disposed on a top redistribution layer (Wu 200)(Wu fig 1), and the die is connected with a metal connection line of the top redistribution layer ((Wu 112, 148)(Wu fig 1).
Regarding claim 2, Wu discloses: The integrated circuit package structure according to claim 1, wherein the at least two redistribution layers (Wu 200, 500) comprise a first redistribution layer (Wu 500) and a second redistribution layer (Wu 200);
the first redistribution layer is disposed on the substrate (Wu fig 1), and a metal connection line of the first redistribution layer (Wu 510, 520, 530, 540, ¶0020, 0057, 0067) is connected with the metal connection line of the substrate (Wu 320, 340A, 340B)(Wu fig 1, ¶0059-0061);
the second redistribution layer is disposed on the first redistribution layer (Wu fig 1, at least indirectly), and a metal connection line of the second redistribution layer (Wu 110, 112 120, 130, 140, 148) is connected with the metal connection line of the first redistribution layer (Wu fig 1, ¶0046).
Regarding claim 3, Wu discloses: The integrated circuit package structure according to claim 2, wherein the first redistribution layer (Wu 500) is provided with a first connection bump (Wu 390, ¶0055), and the first connection bump is connected with the metal connection line of the first redistribution layer (Wu 510, 520, 530, 540)(Wu fig 1, ¶0055), and the metal connection line of the first redistribution layer is connected with the metal connection line of the substrate (Wu 320, 340A, 340B) through the first connection bump (Wu fig 1, ¶0055); and/or
the second redistribution layer (Wu 200) is provided with a second connection bump (Wu 365, ¶0046), and the second connection bump is connected with the metal connection line of the second redistribution layer (Wu 110, 112 120, 130, 140, 148)(Wu fig 1, fig 11, ¶0041-0042, 0046), and the metal connection line of the second redistribution layer is connected with the metal connection line of the first redistribution layer through the second connection bump (Wu fig 1, ¶0010, 0035, 0041, 0048, 0061, 200 is electrically connected to 500 via 300, and 365 and 390).
Regarding claim 4, Wu discloses: The integrated circuit package structure according to claim 2, wherein the first redistribution layer (Wu 500) is provided with a first connection part (Wu 566, ¶0061-0063), and the first connection part is connected with the metal connection line of the first redistribution layer (Wu 510, 520, 530, 540)(Wu fig 1, 18, ¶0061-0063) and bonded to a corresponding connection part (Wu 330A, ¶0043) of the substrate (Wu 300)(Wu fig 1, 15-18, ¶0061-0063); the corresponding connection part of the substrate is connected with the metal connection line of the substrate (Wu 320, 340A, 340B)(Wu fig 1, 10, ¶0043); and/or
the second redistribution layer (Wu 200) is provided with a second connection part (Wu 166, ¶0050), the second connection part is connected with the metal connection line of the second redistribution layer (Wu 110, 112 120, 130, 140, 148)(Wu fig 1, 9, 11, ¶0048-0050), and the second connection part is bonded to a corresponding connection part of the first redistribution layer (Wu 566, ¶0061-0063)(Wu fig 1, 18, ¶0048-0050, 0061-0063, at least indirectly via 300), and the corresponding connection part of the first redistribution layer is connected with the metal connection line of the first redistribution layer (Wu 510, 520, 530, 540)(Wu fig 1, 18, ¶0061-0063).
Regarding claim 5, Wu discloses: The integrated circuit package structure according to claim 1, further comprising: a capacitor (Wu ¶0042), wherein the capacitor and the die (Wu 600) are both disposed on the top redistribution layer (Wu ¶0015); or, the capacitor is disposed on the substrate (Wu 300)(Wu ¶0044).
Regarding claim 6, Wu discloses: An integrated circuit packaging method (Wu figs 1-26, 1, 11, 18), comprising:
disposing at least two redistribution layers (Wu 200, 500, ¶0018-0019) stacked on a surface of a substrate (Wu 300, ¶0018)(Wu fig 1, 11, 18), and connecting a metal connection line (Wu 510, 520, 530, 540, ¶0020, 0057, 0067) of a redistribution layer (Wu 500) adjacent to the substrate (Wu fig 1) with a metal connection line of the substrate (Wu 320, 340A, 340B, ¶0042-0044)(Wu fig 1), and connecting metal connection lines of two adjacent redistribution layers to each other (Wu fig 1, ¶0010, 0017-0020, each at least adjacent to 300);
disposing a die (Wu 600, ¶0014-0015) on a top redistribution layer (Wu 200)(Wu fig 1, ¶0071), and connecting the die with a metal connection line of the top redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032)(Wu fig 1, ¶0071-0073); or,
disposing a die (Wu 600, ¶0014-0015) with a redistribution layer (Wu 610, ¶0015) on the top redistribution layer (Wu 200)(Wu fig 1, ¶0071-0073), and connecting a metal lead (Wu 410, ¶0071-0073) of the redistribution layer of the die with the metal connection line of the top redistribution layer (Wu fig 1, ¶0071-0073).
Regarding claim 7, Wu discloses: The integrated circuit packaging method according to claim 6, wherein the disposing the at least two redistribution layers (Wu 200, 500) stacked on the surface of the substrate (Wu 300)(Wu fig 1) comprises:
disposing a first redistribution assembly (Wu 200, 102, ¶0025) on the surface of the substrate (Wu fig 11, ¶0044), wherein the first redistribution assembly comprises a first temporary carrier (Wu 102, ¶0025) and a first redistribution layer (Wu 200) disposed on and connected to the first temporary carrier (Wu fig 11, ¶0040-0042);
connecting a metal connection line of the first redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032) with the metal connection line of the substrate (Wu 320, 340A, 340B)(Wu fig 1, fig 11, ¶¶0041-0042, 0046);
separating the first temporary carrier from the first redistribution layer (Wu fig 23, ¶0069);
disposing a second redistribution assembly (Wu 500, 502, ¶0057-0064) on the first redistribution layer (Wu fig 17, 18, ¶0061, at least indirectly), wherein the second redistribution assembly comprises a second temporary carrier (Wu 502, ¶0064) and a second redistribution layer (Wu 500) disposed on and connected to the second temporary carrier (Wu fig 17, ¶0064, at least indirectly disposed on and at least electrically connected);
connecting a metal connection line of the second redistribution layer (Wu 510, 520, 530, 540, ¶0020, 0057, 0067) with the metal connection line of the first redistribution layer (Wu fig 1, ¶0010, 0035, 0041, 0048, 0061, 200 is electrically connected to 500 via 300, and 365 and 390);
separating the second temporary carrier from the second redistribution layer (Wu fig 19, ¶0064).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 20210272889 A1, hereafter Wu).
Regarding claim 12, Wu, in at least one embodiment, teaches: An integrated circuit packaging method, comprising:
disposing at least two redistribution layers (Wu 200, 500, ¶0018-0019, of 101A, fig 26) stacked on a first substrate (Wu 300, ¶0018, of 101A, fig 26)(Wu fig 1, 11, 18, 25, 26), and connecting a metal connection line (Wu 510, 520, 530, 540, ¶0020, 0057, 0067, of 101A, fig 26) of a redistribution layer (Wu 500, of 101A, fig 26) adjacent to the first substrate with a metal connection line of the first substrate (Wu 320, 340A, 340B, ¶0042-0044, of 101A, fig 26)(Wu fig 1, 25, 500 is at least vertically adjacent 300), and connecting metal connection lines of two adjacent redistribution layers (Wu 200, 500, of 101A, fig 26, each at least adjacent to 300) to each other (Wu fig 1, ¶0010, 0017-0020, 200 and 500 are at least electrically connected via 300);
disposing a first die (Wu 600, ¶0014-0015) on a top redistribution layer (Wu 200)(Wu fig 1, 26, ¶0071-0073) over the first substrate (Wu 300, 101A), and connecting the first die with a metal connection line of the top redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032)(Wu fig 1, ¶0071-0073) over a surface of the first substrate (Wu fig 1, 26, ¶0073), so as to obtain a first integrated circuit package structure (Wu fig 1, 26, ¶0071-0073);
disposing at least two redistribution layers (Wu 200, 500, ¶0018-0019, of 101B, fig 26) stacked on a second substrate (Wu 300, ¶0018, of 101B, fig 26)(Wu fig 1, 11, 18, 25, 26), and connecting a metal connection line (Wu 510, 520, 530, 540, ¶0020, 0057, 0067, of 101B, fig 26) of a redistribution layer (Wu 500, of 101B, fig 26) adjacent to the second substrate with a metal connection line of the second substrate (Wu 320, 340A, 340B, ¶0042-0044, of 101B, fig 26)(Wu fig 1, 25, 500 is at least vertically adjacent 300), and connecting metal connection lines of two adjacent redistribution layers (Wu 200, 500, of 101B, fig 26, each at least adjacent to 300) to each other (Wu fig 1, ¶0010, 0017-0020, 200 and 500 are at least electrically connected via 300);
wherein the second substrate (Wu 300, ¶0018, of 101B, fig 26) and the first substrate (Wu 300, ¶0018, of 101A, fig 26) are a same substrate (Wu fig 26, 300 is a singular substrate until divided); the redistribution layers on the first substrate and the redistribution layers on the second substrate are different redistribution layers (Wu fig 26).
Wu does not explicitly teach: disposing a second die on a top redistribution layer over the second substrate, and connecting the second die with a metal connection line of the top redistribution layer over a surface of the second substrate, so as to obtain a second integrated circuit package structure; and/or the second die and the first die are different dies.
Wu further teaches: disposing a plurality of dies (Wu 600, ¶0014-0015, ¶0073) on a top redistribution layer (Wu 200)(Wu fig 1, 26, ¶0071-0073) over a substrate (Wu 300, 101A), and connecting a die of the plurality of dies with a metal connection line of the top redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032)(Wu fig 1, ¶0071-0073) over a surface of the substrate (Wu fig 1, 26, ¶0073), so as to obtain a singulated integrated circuit package structure (Wu fig 1, 26, ¶0071-0073).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the steps of disposing the first die of Wu, such that “a second die on a top redistribution layer over the second substrate, and connecting the second die with a metal connection line of the top redistribution layer over a surface of the second substrate, so as to obtain a second integrated circuit package structure; and/or the second die and the first die are different dies”, in order to realize manufacture of multiple singulated packages on a single wafer (Wu ¶0051, 0073).
Regarding claim 13, Wu teaches: The integrated circuit packaging method according to claim 12, wherein the disposing the at least two redistribution layers stacked on the first substrate (Wu 200, 500, of 101A, fig 26) comprises:
disposing a first redistribution assembly (Wu 200, 102, ¶0025, of 101A) on the surface of the first substrate (Wu 300, of 101A)(Wu fig 11, ¶0044), wherein the first redistribution assembly comprises a first temporary carrier (Wu 102, ¶0025, of 101A) and a first redistribution layer (Wu 200, of 101A) disposed on and connected to the first temporary carrier (Wu fig 11, ¶0040-0042);
connecting a metal connection line of the first redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032, of 101A) with the metal connection line of the first substrate (Wu 320, 340A, 340B, of 101A)(Wu fig 1, fig 11, ¶¶0041-0042, 0046);
separating the first temporary carrier from the first redistribution layer (Wu fig 23, ¶0069);
disposing a second redistribution assembly (Wu 500, 502, ¶0057-0064, of 101A) on the first redistribution layer (Wu fig 17, 18, ¶0061, at least indirectly), wherein the second redistribution assembly comprises a second temporary carrier (Wu 502, ¶0064, of 101A) and a second redistribution layer (Wu 500, of 101A) disposed on and connected to the second temporary carrier (Wu fig 17, ¶0064);
connecting a metal connection line of the second redistribution layer (Wu 510, 520, 530, 540, ¶0020, 0057, 0067, of 101A) with the metal connection line of the first redistribution layer (Wu fig 1, ¶0010, 0035, 0041, 0048, 0061, 200 is electrically connected to 500 via 300, and 365 and 390);
separating the second temporary carrier from the second redistribution layer (Wu fig 19, ¶0064).
Regarding claim 14, Wu teaches: The integrated circuit packaging method according to claim 13, wherein the disposing at least two redistribution layers stacked on the second substrate comprises:
disposing a third redistribution assembly (Wu 200, 102, ¶0025, of 101B) on the surface of the second substrate (Wu 300, of 101B)(Wu fig 11, ¶0044), wherein the third redistribution assembly comprises a third temporary carrier (Wu 102, ¶0025, of 101B) and a third redistribution layer (Wu 200, of 101B) disposed on and connected to the third temporary carrier (Wu fig 11, ¶0040-0042);
connecting a metal connection line of the third redistribution layer (Wu 110, 112 120, 130, 140, 148, fig 6, ¶0020, 0022, 0032, of 101B) with the metal connection line of the second substrate (Wu 320, 340A, 340B, of 101B)(Wu fig 1, fig 11, ¶0041-0042, 0046);
separating the third temporary carrier from the third redistribution layer (Wu fig 23, ¶0069);
disposing a fourth redistribution assembly (Wu 500, 502, ¶0057-0064, of 101B) on the third redistribution layer (Wu fig 17, 18, ¶0061, at least indirectly), wherein the fourth redistribution assembly comprises a fourth temporary carrier (Wu 502, ¶0064, of 101B) and a fourth redistribution layer (Wu 500, of 101B) disposed on and connected to the fourth temporary carrier (Wu fig 17, ¶0064);
connecting a metal connection line of the fourth redistribution layer (Wu 510, 520, 530, 540, ¶0020, 0057, 0067, of 101B) with the metal connection line of the third redistribution layer (Wu fig 1, ¶0010, 0035, 0041, 0048, 0061, 200 is electrically connected to 500 via 300, and 365 and 390);
separating the fourth temporary carrier from the fourth redistribution layer (Wu fig 19, ¶0064).
Claims 8-11, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 20210272889 A1, hereafter Wu), as applied to claims 7 or 13 above, and further in view of Lin et al (US 20190380211 A1, hereafter Lin).
Regarding claim 8, Wu discloses: The integrated circuit packaging method according to claim 7, wherein before the disposing the first redistribution assembly (Wu 200, 102, ¶0025) on the surface of the substrate (Wu 300)(Wu fig 11, ¶0044), the integrated circuit packaging method further comprises: prefabricating redistribution assemblies (Wu fig 2-11, 17, ¶0011, 0040, 0078);
wherein the prefabricating the redistribution assemblies comprises:
two or more temporary carriers (Wu 102, 502, ¶0025, 0064);
temporarily generating redistribution layers (Wu 200, 500) on the two or more temporary carriers (Wu fig 2-9, ¶0024, 0056);
Wu does not teach: wherein the prefabricating the redistribution assemblies comprises:
temporarily connecting two or more temporary carriers to a same one initial carrier;
separating the two or more temporary carriers from the initial carrier to obtain at least two redistribution assemblies.
Lin, in the same field of endeavor of semiconductor device manufacturing, teaches: wherein prefabricating redistribution assemblies comprises:
temporarily connecting two or more temporary carriers (Lin 10, ¶0031) to a same one initial carrier (Lin 20, ¶0040)(Lin fig 1D, ¶0041);
temporarily generating redistribution layers (Lin 100’, 130, ¶0036, 0038) on the two or more temporary carriers (Lin fig 1C, ¶0038);
separating the two or more temporary carriers from the initial carrier (Lin fig 1E, ¶0042), so as to obtain at least two redistribution assemblies (Lin 100’, 200)(Lin fig 1H, ¶0049).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Wu to include the steps of Lin in the prefabrication of redistribution assemblies, in order to improve rigidity during manufacture, thereby improving the reliability of the redistribution assemblies (Lin ¶0018, 0060), and/or in order to improve the structural reliability of interconnection pads (Lin ¶0077).
Regarding claim 9, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 8, wherein the temporarily connecting the two or more temporary carriers (Wu 102, 502, similar to Lin 10) to the same one initial carrier (Wu as modified to include Lin 20)(Wu as modified to include Lin, Lin fig 1D, ¶0041) comprises:
temporarily bonding the two or more temporary carriers to the same one initial carrier through a temporary bonding adhesive (Wu 104, Lin 12, ¶0032)(Lin fig 1D, 1E, ¶0042).
Regarding claim 10, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 8, wherein the temporarily generating the redistribution layers (Wu 200, 500, similar to Lin 100’, 130) on the two or more temporary carriers (Wu 102, 502, similar to Lin 10)(Wu as modified to include Lin, Lin fig 1C, ¶0038) comprises:
disposing temporary bonding adhesives (Wu 104, Lin 12, ¶0032) on the two or more temporary carriers (Wu fig 2, Lin fig 1D, 1E, ¶0042);
generating the redistribution layers on the temporary bonding adhesives (Wu fig 9, Lin fig 1C, 1D, ¶0038).
Regarding claim 11, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 8, wherein before the separating the two or more temporary carriers (Wu 102, 502, similar to Lin 10) from the initial carrier (Wu as modified to include Lin 20)(Wu as modified to include Lin, Lin fig 1H, ¶0049), the integrated circuit packaging method further comprises:
disposing connection bumps (Wu 365, 390, ¶0046, 0055) on surfaces of the redistribution layers that are temporarily generated away from the temporary carriers (Wu fig 18, 365 and 390 are disposed on surfaces away from 102 and 502, respectively), wherein the connection bumps are respectively connected with metal connection lines of the redistribution layers (Wu 110, 112 120, 130, 140 of 200, and 510, 520, 530, 540 of 500) that are temporarily generated (Wu fig 1, 18, 0041-0042, 0046, 0055).
Regarding claim 15, Wu teaches: The integrated circuit packaging method according to claim 13, wherein before the disposing the first redistribution assembly (Wu 200, 102, ¶0025, of 101A) on the surface of the first substrate (Wu 300, of 101A)(Wu fig 11, ¶0044), the integrated circuit packaging method further comprises: prefabricating redistribution assemblies (Wu fig 2-11, 17, ¶0011, 0040, 0078);
wherein the prefabricating the redistribution assemblies comprises:
two or more temporary carriers (Wu 102, 502, ¶0025, 0064);
temporarily generating redistribution layers (Wu 200, 500) on the two or more temporary carriers (Wu fig 2-9, ¶0024, 0056);
Wu does not teach: wherein the prefabricating the redistribution assemblies comprises:
temporarily connecting two or more temporary carriers to a same one initial carrier;
separating the two or more temporary carriers from the initial carrier, so as to obtain at least two redistribution assemblies.
Lin, in the same field of endeavor of semiconductor device manufacturing, teaches: wherein prefabricating redistribution assemblies comprises:
temporarily connecting two or more temporary carriers (Lin 10, ¶0031) to a same one initial carrier (Lin 20, ¶0040)(Lin fig 1D, ¶0041);
temporarily generating redistribution layers (Lin 100’, 130, ¶0036, 0038) on the two or more temporary carriers (Lin fig 1C, ¶0038);
separating the two or more temporary carriers from the initial carrier (Lin fig 1E, ¶0042), so as to obtain at least two redistribution assemblies (Lin 100’, 200)(Lin fig 1H, ¶0049).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Wu to include the steps of Lin in the prefabrication of redistribution assemblies, in order to improve rigidity during manufacture, thereby improving the reliability of the redistribution assemblies (Lin ¶0018, 0060), and/or in order to improve the structural reliability of interconnection pads (Lin ¶0077).
Regarding claim 16, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 15, wherein the temporarily connecting the two or more temporary carriers (Wu 102, 502, similar to Lin 10) to the same one initial carrier (Wu as modified to include Lin 20)(Wu as modified to include Lin, Lin fig 1D, ¶0041) comprises:
temporarily bonding the two or more temporary carriers to the same one initial carrier through a temporary bonding adhesive (Wu 104, Lin 12, ¶0032)(Lin fig 1D, 1E, ¶0042).
Regarding claim 17, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 15, wherein the temporarily generating the redistribution layers (Wu 200, 500, similar to Lin 100’, 130) on the two or more temporary carriers (Wu 102, 502, similar to Lin 10)(Wu as modified to include Lin, Lin fig 1C, ¶0038) comprises:
disposing temporary bonding adhesives (Wu 104, Lin 12, ¶0032) on the two or more temporary carriers (Wu fig 2, Lin fig 1D, 1E, ¶0042);
generating the redistribution layers on the temporary bonding adhesives (Wu fig 9, Lin fig 1C, 1D, ¶0038).
Regarding claim 18, Wu in view of Lin teaches: The integrated circuit packaging method according to claim 15, wherein before the separating the two or more temporary carriers (Wu 102, 502, similar to Lin 10) from the initial carrier (Wu as modified to include Lin 20)(Wu as modified to include Lin, Lin fig 1H, ¶0049), the integrated circuit packaging method further comprises:
disposing connection bumps (Wu 365, 390, ¶0046, 0055) on surfaces of the redistribution layers that are temporarily generated away from the temporary carriers (Wu fig 18, 365 and 390 are disposed on surfaces away from 102 and 502, respectively), wherein the connection bumps are respectively connected with metal connection lines of the redistribution layers (Wu 110, 112 120, 130, 140 of 200, and 510, 520, 530, 540 of 500) that are temporarily generated (Wu fig 1, 18, 0041-0042, 0046, 0055).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 20210272889 A1, hereafter Wu) in view of Marimuthu et al (US 20150179570 A1, as cited in the IDS dated 12/19/2025, hereafter Marimuthu).
Regarding claim 19, Wu teaches: A die performance comparison system (Wu ¶0076), comprising:
a first integrated circuit package structure (Wu 100, 101A, fig 1, 26, ¶0014, 0072-0073), wherein the first integrated circuit package structure comprises a first substrate (Wu 300, ¶0018, of 101A, fig 26), at least two redistribution layers (Wu 200, 500, ¶0018-0019, of 101A, fig 26) stacked on the first substrate (Wu fig 1, 11, 18, 25, 26), and a first die (Wu 600, ¶0014-0015) disposed on a top redistribution layer (Wu 200)(Wu fig 1, ¶0071-0073);
a second integrated circuit package structure (Wu 100, 101B, fig 1, 26, ¶0014, 0072-0073), wherein the second integrated circuit package structure comprises a second substrate (Wu 300, ¶0018, of 101B, fig 26), at least two redistribution layers (Wu 200, 500, ¶0018-0019, of 101B, fig 26) stacked on the second substrate (Wu fig 1, 11, 18, 25, 26); wherein the second substrate and the first substrate are a same substrate (Wu fig 26, 300 is a singular substrate until divided); and the redistribution layers on the first substrate and the redistribution layers on the second substrate are different redistribution layers (Wu fig 26, ¶0071-0073); and
a die performance testing device (Wu ¶0076), configured to perform a performance test on the first die in the first integrated circuit package structure (Wu ¶0076).
Wu does not explicitly teach: a second die disposed on a top redistribution layer; and/or the second die and the first die are different dies.
Wu further teaches: a plurality of dies (Wu 600, ¶0014-0015, ¶0073) disposed on a top redistribution layer (Wu 200)(Wu fig 1, 26, ¶0071-0073), wherein the dies are different dies (¶0071-0073).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first die of Wu, such that “a second die disposed on a top redistribution layer”, in order to realize manufacture of multiple singulated packages on a single wafer (Wu ¶0051, 0073).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first die of Wu for each singulated package, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Wu does explicitly teach: the die performance testing device is configured to perform a performance test on the first die in the first integrated circuit package structure and the second die in the second integrated circuit package structure, respectively, so that a data analysis apparatus compares performance of the first die and the second die according to data obtained from the performance test.
Marimuthu, in the same field of endeavor of semiconductor device manufacturing, teaches: a die performance testing device (Marimuthu 136, 138, ¶0045-0046) is configured to perform a performance test on a first die (Marimuthu 124, ¶0046)(Marimuthu fig 3c, ¶0046) in a first integrated circuit package structure (Marimuthu 220, 538, ¶0135-0039, fig 4m) and a second die (Marimuthu 124, ¶0046, multiple instances of 124) in a second integrated circuit package structure (Marimuthu 220, ¶0135-0039, fig 4m, multiple instances of 124 within multiple 220)(Marimuthu fig 3c, ¶0046), respectively, so that a data analysis apparatus (Marimuthu 140, ¶0046) compares performance of the first die and the second die according to data obtained from the performance test (Marimuthu ¶0046, 0084, “compared to an expected response to test functionality of the semiconductor die”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Wu to include the die performance testing as taught by Marimuthu, such that “the die performance testing device is configured to perform a performance test on the first die in the first integrated circuit package structure and the second die in the second integrated circuit package structure, respectively, so that a data analysis apparatus compares performance of the first die and the second die according to data obtained from the performance test”, in order to ensure that only known good dies are included in the manufacture of the semiconductor packaging (Marimuthu ¶0046), thereby prevent waste in manufacturing and materials due to a defective die (Marimuthu ¶0085).
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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