DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on October 1, 2024 has been reviewed by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0060844 A1 (Miyairi) in view of Jin et al., “Optimization of Saddle Junctionless FETs for Extreme High Integration”, May 23, 2016, Springer Science+Business Media New York, J Comput Electron, 15, pages 801-808 (Jin).
Regarding claim 1, Miyairi discloses, A semiconductor device comprising a first transistor (FIG. 1B) comprising:
a first metal oxide (first metal oxide (136); FIGs. 4A and 4B; [0179] and [0128]) comprising a first depressed portion (annotated FIG. 4B, below) and a second depressed portion (annotated FIG. 4B, below);
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a first conductor (first conductor (137); annotated FIG. 5A, below; [0187]) in the first depressed portion (annotated FIG. 4B, above); and
a second conductor (second conductor (137); annotated FIG. 5A, below; [0187]) in the second depressed portion (annotated FIG. 4B, above);
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wherein a top surface (annotated FIG. 5A, above) of the first conductor (137; annotated FIG. 5A, above) and a top surface (annotated FIG. 5A, above) of the second conductor (137; annotated FIG. 5A, above) are each level with or substantially level1 with a top surface (annotated FIG. 5A, above) of the first metal oxide (136).
But, Miyairi does not appear to explicitly disclose, a third depressed portion between the first depressed portion and the second depressed portion;
a first insulator in the third depressed portion and over the first metal oxide; and
a third conductor over the first insulator, the third conductor overlapping with the first metal oxide with the first insulator therebetween.
However, in analogous art, Jin discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor device comprising a saddle junctionless field effect transistor (page 801; FIGs. 1(a) and 1(b)) can be predicably fabricated to include a depressed portion (annotated FIGs 1(a) and 1(b), below) in a semiconductor material (annotated FIGs 1(a) and 1(b), below) where the depressed portion is located between a source contact (FIGs. 1(a) and 1(b)) and a drain contact (FIGs. 1(a) and 1(b)). Jin also discloses an insulator (annotated FIGs 1(a) and 1(b), below) in the depressed portion over the semiconductor material (annotated FIGs 1(a) and 1(b), below) and a conductor (conductor (Gate); FIGs. 1(a) and 1(b)) over the insulator (annotated FIGs 1(a) and 1(b), below), the conductor (gate) overlapping with the semiconductor material (annotated FIGs 1(a) and 1(b), below) with the insulator (annotated FIGs 1(a) and 1(b), below) therebetween. Jin additionally discloses that because there is no doping concentration throughout the entirety of a saddle junctionless field effect transistor the fabrication difficulty is reduced (e.g., lower thermal budget and ultra-fast annealing techniques) compared to conventional P-N junction-based MOSFETs which makes it a strong candidate of extremely scaled cells for next-generation integrated circuits (page 801).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Miyairi and Jin before him/her to fabricate a third depressed portion in first metal oxide (136) between the first depressed portion (annotated FIG. 4B, above) of Miyairi (which can act as a source) and the second depressed portion (annotated FIG. 4B, above) of Miyairi (which can act as a drain), as taught by Jin, and include a first insulator in the third depressed portion and over the first metal oxide (136) of Miyairi and a third conductor over the first insulator, as also taught by Jin, the third conductor overlapping with the first metal oxide (136) with the first insulator therebetween (which can act as a gate), to form a saddle junctionless transistor, as additionally taught by Jin, thereby reducing fabrication difficultly of the first transistor of Miyairi because there is no doping concentration throughout the entirety thereof, as further taught by Jin.
Regarding claim 4, Miyairi in view of Jin discloses, The semiconductor device according to claim 1,
wherein a bottom surface of the first depressed portion (Jin, annotated FIG. 1(a), above) is level with or substantially level with a bottom surface (Jin, annotated FIG. 1(a), above) of the third depressed portion (Jin, annotated FIG. 1(a), above), and
wherein a bottom surface of the second depressed portion (Jin, annotated FIG. 1(a), above) is level with or substantially level with the bottom surface (Jin, annotated FIG. 1(a), above) of the third depressed portion (Jin, annotated FIG. 1(a), above).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Miyairi in view of Jin and further in view of US 2020/0411676 A1 (Chang).
Regarding claim 5, Miyairi in view of Jin does not appear to explicitly disclose, wherein a bottom surface of the first depressed portion is closer to a top surface side of the first metal oxide than a bottom surface of the third depressed portion, and
wherein a bottom surface of the second depressed portion is closer to a top surface side of the first metal oxide than the bottom surface of the third depressed portion.
However, in analogous art, Chang discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a saddle gate transistor (saddle gate (100); FIG.1; [0017] and [0024]) having a gate (gate (G1); FIG. 2; [0019]) may be predicably fabricated so a bottom surface of a first depressed portion (annotated FIG. 2, below) is closer to a top surface side (annotated FIG. 2, below) of semiconductor (semiconductor (102); FIG. 2; [0017]) than a bottom surface of a third depressed portion (annotated FIG. 2, below). Chang also discloses that a bottom surface of a second depressed portion (annotated FIG. 2, below) may be predicably fabricated to be closer to a top surface side (annotated FIG. 2, below) of semiconductor (102) than a bottom surface of the third depressed portion (annotated FIG. 2, below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Miyairi, Jin, Chang before him/her that a bottom surface of the first depressed portion (Miyairi, annotated FIG. 4B, above) could be predicably fabricated to be closer to a top surface side (Miyairi, FIG. 5A) of the first metal oxide (136) than a bottom surface of the third depressed portion of Miyairi in view of Jin, as taught by Chang, and that a bottom surface of the second depressed portion (Miyairi, annotated FIG. 4B, above) could be predicably fabricated to be closer to a top surface side (Miyairi, FIG. 5A) of the first metal oxide (136) than the bottom surface of the third depressed portion of Miyairi in view of Jin, as also taught by Chang, with no change in the function of the first, second, and third depressed portions because the respective first, second and third conductors, as well as the first insulator in third depressed portion, could still be located therein. Please see, MPEP 2143(A).
Allowable Subject Matter
Claims 2, 3, and 6-12 are allowed. Following is an Examiner’s statement of reasons for allowance.
Regarding claim 2—The combination of Miyairi in view of Jin discloses a first transistor (Miyairi, first transistor (1142); FIGs 1B and 30B; [0357]) and a second transistor (Miyairi, second transistor (1142); FIGs 1B and 30B; [0357]) adjacent to each other. Miyairi in view of Jin also discloses that the first transistor includes the recited features of claim 1 ([0357]), as detailed above. Miyairi in view of Jin additionally discloses that the first metal oxide (136) of the first transistor (1142) and a second metal oxide (Miyairi, second metal oxide (136); FIGs. 4A and 4B; [0179] and [0128]) of the second transistor (1142) are over a second insulator (Miyairi, second insulator (102); FIG. 5A; [0126]). However, the combination of Miyairi in view of Jin does not appear to explicitly disclose: (i) a third insulator over the first metal oxide and the second metal oxide that includes an opening portion overlapping with the third depressed portion, (ii) that the first insulator and the third conductor are in the opening portion of the third insulator, (iii) a fourth insulator between the first metal oxide and the second metal oxide in a top view of the semiconductor device, and (iv) a top surface of the first conductor, a top surface of the second conductor, and a top surface of the first metal oxide are each level with or substantially level with a top surface of the fourth insulator. Claims 7-9 are allowable because they depend from claim 2.
Regarding claim 3—The combination of Miyairi in view of Jin does not appear to disclose that bottom surfaces of the first and second depressed portions (Miyairi, annotated FIG. 4B, above) are closer to a bottom surface side of the first metal oxide (136) than a bottom surface of the third depressed portion (Jin, annotated FIGs. 1(a) and 1(b), above). Claims 10-12 are allowable because they depend from claim 3.
Regarding claim 6—The combination of Miyairi in view of Jin does not appear to disclose a first transistor (Miyairi, first transistor (1142); FIGs 1B and 30B; [0357]) that includes the recited features of claim 1, as detailed above. Miyairi in view of Jin additionally discloses that the first metal oxide (136) is over a second insulator (Miyairi, second insulator (102); FIG. 5A; [0126]). However, the combination of Miyairi in view of Jin does not appear to explicitly disclose: (i) a third insulator is over the first metal oxide and includes an opening portion overlapping with the third depressed portion, (ii) the first insulator and the third conductor are in the opening portion of the third insulator, (iii) the first metal oxide is surrounded by a fourth insulator in a top view of the semiconductor device, and (iv) a top surface of the first conductor, a top surface of the second conductor, and a top surface of the first metal oxide are each level with or substantially level with a top surface of the fourth insulator.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2022/0199663 A1 (Gao)—Discloses that a saddle-gate transistor (FIG. 3A) was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see paragraph [0042] of Applicant’s specification regarding the meaning of the recited limitation of “substantially level”.
Prosecution Insights