DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant's election with traverse of Group I (claims 1-13 and 20) in the reply filed on 8/7/2026 is acknowledged. In the reply, Applicant amended claim 14 to include the limitation that the original layers and the modified layers have different light reflectivities, thereby addressing the basis for the restriction between Group I and Group II. Claims 15-19 depend from amended claim 14.
The traverse is persuasive. Accordingly, the restriction requirement is currently Withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 11/27/2024 and IDS filed on 3/17/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 14 is objected to because of the following informalities:
In claim 14, line 9, “sequentially applying laser to” should read --sequentially applying a laser to-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xue et al. (CN 114709319A; hereinafter ‘Xue’) in view of Wu et al. (CN 107538136A; hereinafter ‘Wu’).
Regarding claim 1, Xue teaches a chip structure (a grain including a light-emitting chip 5 and a color conversion region 2, FIG. 11, [0066]) comprising:
a chip wafer unit (a chip wafer unit including 5 and U-GaN layer 42, FIGS. 8-11, [0053, 0057, 0062]; hereinafter ‘CWU’) and
a color conversion unit (a color conversion unit including 2 and a sapphire substrate 11, [0032, 0044]; hereinafter ‘CCU’) disposed on a light exit side of the chip wafer unit (CCU is bonded to the light-emitting surface of CWU, [0015, 0021]) wherein
the color conversion unit (CCU) includes a base substrate (11) include a body portion (a central portion of 11 corresponding to 2 and 5; hereinafter ‘11-B’) and an edge portion (a peripheral portion of 11 surrounding 11-B; hereinafter ‘11-E’) surrounding the body portion (11-E surrounding 11-B, FIG. 11);
the first direction (the thickness direction; hereinafter ‘D1’) being perpendicular to a surface of the base substrate away from the chip wafer unit (D1 being perpendicular to a surface of 11 away from CWU, FIG. 11).
Xue does not teach that the edge portion includes original layers and modified layers alternately arranged along a first direction; in the edge portion, layers located on outermost two sides in the first direction are both original layers; and a light reflectivity of the original layers and a light reflectivity of the modified layers are different.
Wu teaches a chip structure (LED chips comprising sapphire substrates, FIGS. 1-3, [0017, 0031-0033, 0038-0041]) comprising:
a base substrate (sapphire substrate, FIG. 3, [0037]; hereinafter ‘SS’) includes
the edge portion (an edge portion is peripheral portions of SS adjacent to the intersecting X-direction and Y-direction cutting paths, FIGS. 1-3, [0031-0033, 0047-0049]; hereinafter ‘SS-E’) includes original layers (original layers are the unmodified sapphire portions remaining between and outside modified layers 2, FIG. 2, [0021, 0025-0026, 0031]; hereinafter ‘SS-O’) and modified layers (laser modified layers 2 formed at spaced-apart focal depths inside 4, FIG. 2, [0021, 0025-0026, 0031]) alternately arranged along a first direction (SS-O and 2 alternately arranged along the thickness direction, FIG. 2);
in the edge portion (SS-E), layers located on outermost two sides in the first direction are both original layers (the internally formed modified layers 2 leave SS-O between the outermost modified layers 2 and the opposing surfaces of SS, FIG. 2, [0021, 0025-0026]); and
a light reflectivity of the original layers and a light reflectivity of the modified layers are different (modified layer 2 are regions around the laser energy points where the sapphire crystal structure is destroyed, while SS-O retains the original sapphire crystal structure; therefore, modified layers 2 and SS-O predictably exhibit different optical properties, including different light reflectivities, [0021, 0031]).
It would have been obvious to apply Wu’s multi-focus laser cutting technique to sapphire substrate 11 of Xue’s color conversion unit to provide the chip structure comprising: the base substrate includes the edge portion includes original layers and modified layers alternately arranged along a first direction; in the edge portion, layers located on outermost two sides in the first direction are both original layers; and a light reflectivity of the original layers and a light reflectivity of the modified layers are different as claimed, because Xue teaches cutting the sapphire containing color conversion structure into individual units, and Wu teaches that forming modified layers at multiple depths within a sapphire substrate facilitates reliable separation of the substrate while reducing twinning, oblique cracking, edge chipping, and other cutting defects, thereby improving cutting yield and edge quality (Xue, [0032, 0062-0067]; Wu, [0017, 0031-0033, 0041]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Xue due to above reason.
Regarding claim 2, Xue in view of Wu teaches the chip structure according to claim 1, Xue does not teach the chip structure wherein the body portion and the original layers have the same light reflectivity.
Wu teaches the chip structure wherein the body portion (a body portion is an unmodified central portion of sapphire substrate wafer 4 remaining after separation along the cutting paths, FIGS. 1-3, [0031-0033]; hereinafter ‘SS-B’) and the original layers (SS-O) have the same light reflectivity (SS-B and SS-O are both unmodified portions of the same sapphire substrate SS that retain the original sapphire crystal structure and therefore predictably have the same light reflectivity, FIG. 1-2, [0021, 0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the chip structure wherein the body portion and the original layers have the same light reflectivity as claimed, because limiting laser-induced crystal damage to the modified layers preserves the optical performance and brightness of the chip while facilitating substrate separation [0011, 0031-0033].
Regarding claim 3, Xue in view of Wu teaches the chip structure according to claim 1, wherein
the base substrate (Xue: 11, FIG. 11) includes
a first surface and a second surface opposite to each other in the first direction (11 includes the outer surface and inner surface, respectively, which are opposite to each other along the thickness direction D1, FIG. 11), and
a plurality of side surfaces connecting the first surface and the second surface (the sides surfaces of 11 connecting the outer surface and the inner surface, FIG. 11)
the second surface is closer to the chip wafer unit than the first surface (the inner surface of 11 is closer to CWU than the opposing outer surface, FIG. 11).
Xue does not teach the chip structure wherein the edge portion includes a plurality of sub-portions that are respectively arranged corresponding to the plurality of side surfaces; a number of modified layers included in each of the plurality of sub-portions is the same; or the number of modified layers included in each of the plurality of sub-portions is not necessarily the same.
Wu teaches the chip structure wherein
the edge portion (SS-E, FIG. 2) includes
a plurality of sub-portions that are respectively arranged corresponding to the plurality of side surfaces (SS-E includes peripheral sub-portions respectively extending along the side surfaces formed by the intersection X-direction and Y-direction cutting paths, FIGS. 1-2, [0031-0032]);
a number of modified layers included in each of the plurality of sub-portions is the same (each peripheral sub-portion formed along the cutting paths includes the same number of modified layers 2 formed at the same multiple focal depths, FIGS. 1-2, [0021, 0025, 0031]); or
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the chip structure wherein the edge portion includes a plurality of sub-portions that are respectively arranged corresponding to the plurality of side surfaces; a number of modified layers included in each of the plurality of sub-portions is the same; or the number of modified layers included in each of the plurality of sub-portions is not necessarily the same as claimed, because consistently applying the same multi-focus laser cutting process along the boundaries of each chip provides uniform crack formation and reliable separation around the chip while reducing cutting defect [0031-0033].
Regarding claim 4, Xue in view of Wu teaches the chip structure according to claim 3, Xue does not teach the chip structure wherein at least one sub-portion among the plurality of sub-portions includes N modified layers, N is a positive integer, and N >2; a modified layer farthest from the chip wafer unit is a first modified layer, and a distance between the first modified layer and the first surface is greater than a distance between any two adjacent modified layers; and/or a modified layer closest to the chip wafer unit is an Nth modified layer, and a distance between the Nth modified layer and the second surface is greater than the distance between any two adjacent modified layers.
Wu teaches the chip structure wherein
at least one sub-portion among the plurality of sub-portions includes N modified layers, N is a positive integer, and N >2 (in a 200 µm-thick sapphire substrate SS, a first modified layer is formed at approximately 1/3 to 2/5 of the thickness of SS, i.e., 66.7-80 µm from the electrode surface 3 corresponds to the claimed the second surface and additional modified layers are formed at intervals 20-25 µm toward the first surface, thereby providing at least 5 modified layers within SS, [0026, 0055]);
a modified layer closest to the chip wafer unit is an Nth modified layer, and a distance between the Nth modified layer and the second surface is greater than the distance between any two adjacent modified layers (the first modified layer corresponds to the claimed Nth modified layer and is spaced approximately 66.7-80 µm from the second surface, which is greater than the 20-25 µm spacing between adjacent modified layers, [0026, 0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the chip structure wherein at least one sub-portion among the plurality of sub-portions includes N modified layers, N is a positive integer, and N >2; a modified layer farthest from the chip wafer unit is a first modified layer, and a distance between the first modified layer and the first surface is greater than a distance between any two adjacent modified layers; and/or a modified layer closest to the chip wafer unit is an Nth modified layer, and a distance between the Nth modified layer and the second surface is greater than the distance between any two adjacent modified layers as claimed, because forming modified layers at multiple depths allows the resulting stress-release cracks to connect through t relatively thick sapphire substrate, thereby facilitating reliable separation and reducing cutting defects [0017, 0031-0033].
Regarding claim 5, Xue in view of Wu teaches the chip structure according to claim 4, Xue does not teach the chip structure wherein the distance between the first modified layer and the first surface is in a range of 15 μm to 35 μm, inclusive; and/or the distance between the Nth modified layer and the second surface is in a range of 15 μm to 35 μm, inclusive.
Wu teaches the chip structure wherein
the distance between the first modified layer and the first surface is in a range of 15 μm to 35 μm, inclusive (for a 200 µm-thick sapphire substrate SS, the first modified layer is formed at approximately 66.7 µm from the second surface, corresponding to 1/3 of the substrate thickness, and additional modified layers are formed at 20 µm intervals toward the first surface; 6 modified layers are thereby positioned at approximately 66.7, 86.7, 106.7, 126.7, 146.7, and 166.7 µm from the second surface, leaving a distance of approximately 33.3 µm between the modified layer farthest from the chip wafer unit and the first surface, which is within the claimed range of 15-35 µm, [0026, 0055]); and/or
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the chip structure wherein the distance between the first modified layer and the first surface is in a range of 15 μm to 35 μm, inclusive; and/or the distance between the Nth modified layer and the second surface is in a range of 15 μm to 35 μm, inclusive as claimed, because using multiple modified layers at regular intervals through a relative thick sapphire substrate promotes connection of stress-release cracks for reliable separation while leaving an unmodified surface portion that limits surface damage and cutting defect [0031-0033].
Regarding claim 6, Xue in view of Wu teaches the chip structure according to claim 4, Xue does not teach the chip structure wherein the distance between the first modified layer and the first surface is greater than or equal to 20 μm; and/or the distance between the Nth modified layer and the second surface is greater than or equal to 20 μm.
Wu teaches the chip structure wherein
the distance between the first modified layer and the first surface is greater than or equal to 20 μm (for a 200 µm-thick sapphire substrate SS, when the modified layer closest to the second surface is formed at approximately 66.7 µm from the second surface and 5 additional modified layers are formed at 20 µm intervals toward the first surface; the first modified layer is positioned approximately 33.3 µm from the first surface, which is greater than 20 μm, [0026, 0055]); and/or
the distance between the Nth modified layer and the second surface is greater than or equal to 20 μm (for a 200 µm-thick sapphire substrate SS, the Nth modified layer, which is the modified layer closest to the second surface, is positioned approximately 66.7 µm from the second surface, which is greater than 20 μm, [0026, 0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the chip structure wherein the distance between the first modified layer and the first surface is greater than or equal to 20 μm; and/or the distance between the Nth modified layer and the second surface is greater than or equal to 20 μm as claimed, because maintaining sufficient unmodified sapphire margins adjacent to the opposing surfaces reduces laser-induced surface damage and edge chipping while permitting cracks originating from the internally formed modified layers to propagate reliably through the sapphire substrate during separation [0031-0033].
Regarding claim 14, Xue teaches a method for manufacturing a chip structure, comprising:
forming an initial wafer (wafer 4, FIG. 5, [0051]), the initial wafer (4) including
a plurality of chip wafer units (a chip wafer unit including multiple light-emitting chips 5 and U-GaN layer 42, FIG. 6, [0053]; hereinafter ‘CWU’);
forming a color conversion substrate (porous structure 1, FIG. 1, [0032]), wherein the color conversion substrate (1) includes
a base substrate motherboard (sapphire substrate 11, FIG. 3, [0032]) and
a plurality of color conversion structures (multiple color conversion regions 2, FIG. 3, [0044]) disposed on the base substrate motherboard (11), and
each color conversion structure (2) and a portion of the base substrate motherboard (11) corresponding thereto constitute a color conversion unit (a color conversion unit including 2 and 11, FIG. 3; hereinafter ‘CCU’);
coupling the color conversion substrate (1) to the initial wafer (4) to obtain a coupling structure (a coupling structure including CWU and CCU, FIG. 9), each chip wafer unit (CWU) being arranged opposite to one color conversion unit (CCU); and
sequentially cutting the base substrate motherboard (11, FIG. 11, [0066]), wherein the first direction (the thickness direction; hereinafter ‘D1’) being perpendicular to a surface of the base substrate motherboard away from the plurality of color conversion structures (D1 being perpendicular to a surface of 11 away from 2, FIG. 11);
the base substrate motherboard (11) is cut to form a plurality of base substrates (a plurality of individual base substrates obtained by cutting 11, FIG. 11; hereinafter ‘11p’), each base substrate (11p) includes
a body portion (a central portion of 11p corresponding to 2 and 5; hereinafter ‘11p-B’)and
an edge portion (a peripheral portion of 11p surrounding 11p-B; hereinafter ‘11p-E’) surrounding the body portion (11p-E surrounding 11p-B, FIG. 11).
Xue does not teach the method for manufacturing a chip structure comprising: sequentially applying laser to a plurality of focuses inside the base substrate motherboard for cutting, wherein the plurality of focuses are arranged sequentially in a first direction, the edge portion includes original layers and modified layers alternately arranged along the first direction, and layers located on outermost two sides in the first direction are both original layers; and a light reflective of the original layers and a light reflectivity of the modified layers are different.
Wu teaches a method for manufacturing a chip structure [0019] comprising:
sequentially applying laser to a plurality of focuses inside the base substrate motherboard for cutting (using an ultraviolet laser scribing machine to a plurality of focuses inside sapphire substrate, hereinafter ‘SS’, for cutting, FIG. 2, [0020]), wherein
the plurality of focuses are arranged sequentially in a first direction (the plurality of focuses are arranged sequentially in the thickness direction, FIG. 2, [0021]),
the edge portion (an edge portion is peripheral portions of SS adjacent to the intersecting X-direction and Y-direction cutting paths, FIGS. 1-3, [0031-0033, 0047-0049]; hereinafter ‘SS-E’) includes
original layers (original layers are the unmodified sapphire portions remaining between and outside modified layers 2, FIG. 2, [0021, 0025-0026, 0031]; hereinafter ‘SS-O’) and
modified layers (laser modified layers 2 formed at spaced-apart focal depths inside 4, FIG. 2, [0021, 0025-0026, 0031])
alternately arranged along the first direction (SS-O and 2 alternately arranged along the thickness direction, FIG. 2), and
layers located on outermost two sides in the first direction are both original layers (the internally formed modified layers 2 leave SS-O between the outermost modified layers 2 and the opposing surfaces of SS, FIG. 2, [0021, 0025-0026]); and
a light reflective of the original layers and a light reflectivity of the modified layers are different (modified layer 2 are regions around the laser energy points where the sapphire crystal structure is destroyed, while SS-O retains the original sapphire crystal structure; therefore, modified layers 2 and SS-O predictably exhibit different optical properties, including different light reflectivities, [0021, 0031]).
It would have been obvious to apply Wu’s multi-focus laser cutting technique to sapphire substrate 11 of Xue’s color conversion unit to provide the method for manufacturing a chip structure comprising: sequentially applying laser to a plurality of focuses inside the base substrate motherboard for cutting, wherein the plurality of focuses are arranged sequentially in a first direction, the edge portion includes original layers and modified layers alternately arranged along the first direction, and layers located on outermost two sides in the first direction are both original layers; and a light reflective of the original layers and a light reflectivity of the modified layers are different as claimed, because Xue teaches cutting the sapphire containing color conversion structure into individual units, and Wu teaches that forming modified layers at multiple depths within a sapphire substrate facilitates reliable separation of the substrate while reducing twinning, oblique cracking, edge chipping, and other cutting defects, thereby improving cutting yield and edge quality (Xue, [0032, 0062-0067]; Wu, [0017, 0031-0033, 0041]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Xue due to above reason.
Regarding claim 16, Xue in view of Wu teaches the method according to claim 14, Xue does not teach the method wherein the base substrate motherboard includes a plurality of cutting lanes, and the laser cuts along the cutting lanes; when the laser cuts each of the cutting lanes, a number of focuses to which the laser is applied is the same or not necessarily the same.
Wu teaches the method wherein the base substrate motherboard (SS, FIG. 2) includes a plurality of cutting lanes (a plurality of cutting lanes aligned with respective grooves 1, [0047]; hereinafter ‘CL’) and the laser cuts along the cutting lanes (the laser cuts along each CL, FIG. 2);
when the laser cuts each of the cutting lanes (the laser cuts each of CL), a number of focuses to which the laser is applied is the same or not necessarily the same (the laser is applied to the same number of focal points along each CL, FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the method wherein the base substrate motherboard includes a plurality of cutting lanes, and the laser cuts along the cutting lanes; when the laser cuts each of the cutting lanes, a number of focuses to which the laser is applied is the same or not necessarily the same as claimed, because applying the multi-focus laser cutting process along each cutting lane improves the cutting yield of the substrate and avoids twinning, edge chipping, and oblique cracks [0017, 0033].
Regarding claim 17, Xue in view of Wu teaches the method according to claim 14, Xue does not teach the method wherein a number of the plurality of focuses is N, N is a positive integer, and N≥2; a focus farthest from the initial wafer is a first focus, and a focus closest to the initial wafer is an Nth focus; a surface of the base substrate motherboard away from the initial wafer is a first surface, and a surface of the base substrate motherboard close to the initial wafer is a second surface; a distance between the first focus and the first surface is greater than or equal to a distance between any two adjacent focuses; and/or a distance between the Nth focus and the second surface is greater than or equal to the distance between any two adjacent focuses.
Wu teaches the method wherein
a number of the plurality of focuses is N, N is a positive integer, and N≥2 (the number of focuses is 2, [0025]);
a focus farthest from the initial wafer is a first focus (a first focus at which the second modified layer is formed; hereinafter ‘F-1’), and
a focus closest to the initial wafer is an Nth focus (a Nth focus at which the first modified layer is formed; hereinafter ‘F-2’);
a surface of the base substrate motherboard away from the initial wafer is a first surface (substrate surface, FIG. 2, [0048]; hereinafter ‘3R’), and a surface of the base substrate motherboard close to the initial wafer is a second surface (electrode surface 3 corresponding to the LED device side of SS, FIG. 2, [0005, 0020, 0047-0048]).
a distance between the Nth focus and the second surface is greater than or equal to the distance between any two adjacent focuses (the distance between F-2 and electrode surface 3 is 20-100 µm, which is greater than or equal the distance of 20 µm between F-1 and F-2, [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the method wherein a number of the plurality of focuses is N, N is a positive integer, and N≥2; a focus farthest from the initial wafer is a first focus, and a focus closest to the initial wafer is an Nth focus; a surface of the base substrate motherboard away from the initial wafer is a first surface, and a surface of the base substrate motherboard close to the initial wafer is a second surface; a distance between the first focus and the first surface is greater than or equal to a distance between any two adjacent focuses; and/or a distance between the Nth focus and the second surface is greater than or equal to the distance between any two adjacent focuses as claimed, because arranging multiple laser focuses at controlled depths and intervals facilitates connection of cracks between adjacent modified layers, thereby enabling reliable separation of a thick substrate while improving cutting yield and reducing defects such as oblique cracks and edge chipping [0029, 0031-0033].
Regarding claim 18, Xue in view of Wu teaches the method according to claim 17, Xue does not teach the method wherein the distance between the first focus and the first surface is in a range of 15 μm to 35 μm, inclusive; and/or the distance between the Nth focus and the second surface is in a range of 15 μm to 35 μm, inclusive.
Wu teaches the method wherein
the distance between the Nth focus and the second surface is in a range of 15 μm to 35 μm, inclusive (the distance between F-2 and electrode surface 3 is 20-100 μm, [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the method wherein the distance between the first focus and the first surface is in a range of 15 μm to 35 μm, inclusive; and/or the distance between the Nth focus and the second surface is in a range of 15 μm to 35 μm, inclusive as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed range overlaps or lies within a range disclosed by the prior art, a prima facie case of obviousness exists. MPEP §2144.05.
Claims 7-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A) as applied to claim 1 above, and further in view of Li et al. (CN 113725249A; hereinafter ‘Li’).
Regarding claim 7, Xue in view of Wu teaches the chip structure according to claim 1, wherein the color conversion unit (Xue: CCU, FIG. 11) further includes:
a defining dam layer (a defining dam layer is a portion of second layer 12 surrounding the plurality of holes, FIGS. 1 and 2, [0031-0034]; hereinafter ‘DDL’) including a plurality of opening regions (DDL including a plurality of opening regions, [0032]); and
a color conversion layer (2, FIG. 3, [0044]) arranged in the same layer as the defining dam layer (2 is formed by filling the plurality of holes of 12 with quantum dots thus 2 is arranged in the same layer as the DDL, FIGS. 1-3).
Xue in view of Wu does not teaches the chip structure, wherein the color conversion unit further includes: a color filter layer disposed on a side of the base substrate facing the chip wafer unit and including a black matrix and a plurality of filter portions defined by the black matrix, an orthographic projection of the black matrix on the base substrate being located within a range enclosed by the edge portion; a defining dam layer disposed on a side of the color filter layer away from the base substrate and including a plurality of opening regions, the plurality of opening regions being in one-to-one correspondence with the plurality of filter portions.
Li teaches a chip structure (FIG. 3, [0169]), wherein the color conversion unit (a color conversion layer cover plate 30 including colorless PI 31, black matrix BM 32, filter portions 33, first defining dam 34, and color conversion portions 35, FIGS. 3 and 6a-6d, [0094-0097, 0144-0150];) further includes:
a color filter layer (a color filter layer including BM 32 and 33, FIGS. 3 and 6a, [0121, 0145-0147]; hereinafter ‘CFL’)
disposed on a side of the base substrate facing the chip wafer unit (CFL disposed on a side of PI 31 facing the epitaxial wafter 10, FIGS. 1-3, [0094]) and
including a black matrix (BM 32) and a plurality of filter portions (red, green, and blue filter films 33) defined by the black matrix (33 defined by BM32, Figure 6a);
a defining dam layer (34) disposed on a side of the color filter layer away from the base substrate (34 disposed on a side of CFL away from PI 31, FIG. 3, [0121]) and
including a plurality of opening regions (34 including first, second, and third opening regions, FIGS. 3 and 6b, [0095]; hereinafter ‘34-O’),
the plurality of opening regions being in one-to-one correspondence with the plurality of filter portions (34-O corresponding to the red, green, and blue filter films 33 and respectively receiving a red quantum dot conversion portion, a green quantum dot conversion portion, and a scattering particle portion, FIGS. 3 and 6a-6c, [0096-0097, 0121, 0145-0149]).
Li does not explicitly disclose that an orthographic projection of the black matrix on the base substrate being located within a range enclosed by the edge portion.
However, Li’s color filter structure is incorporated into Xue’s color conversion unit including the sapphire substrate, as modified by Wu to include the claimed edge portion, it would have been obvious to dispose Li’s black matrix BM 32 and filter portions 33 over the body region of the sapphire substrate corresponding to the functional sub-pixel region. Accordingly, an orthographic projection of the black matrix BM 32 on the sapphire substrate would be located within the range enclosed by the edge portion.
As taught by Li, one of ordinary skill in the art would utilize and modify the above teaching into Xue in view of Wu to obtain and achieve the chip structure, wherein the color conversion unit further includes: a color filter layer disposed on a side of the base substrate facing the chip wafer unit and including a black matrix and a plurality of filter portions defined by the black matrix, an orthographic projection of the black matrix on the base substrate being located within a range enclosed by the edge portion; a defining dam layer disposed on a side of the color filter layer away from the base substrate and including a plurality of opening regions, the plurality of opening regions being in one-to-one correspondence with the plurality of filter portions as claimed, because the black matrix optically separates the respective filter portions and the color filter layer further filters the light emitted from the color conversion layer, thereby reducing color crosstalk between adjacent sub-pixels and improving the display effect [0121-0122].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Li in combination with Xue in view of Wu due to the above reason.
Regarding claim 8, Xue in view of Wu and Li teaches the chip structure according to claim 7, but Xue in view of Wu does not teach the chip structure wherein the plurality of opening regions include a first-type opening region and a second-type opening region; the color conversion layer includes a color conversion portion and a filling portion; the color conversion portion is arranged in the first-type opening region, and the filling portion is arranged in the second-type opening region; the color conversion portion includes a quantum dot conversion portion or a fluorescent color conversion portion; and the filling portion includes a scattering particle portion or transparent glue.
Li teaches the chip structure wherein
the plurality of opening regions (34-O, FIGS. 3 and 6b) include
a first-type opening region (the first and second opening regions; hereinafter ‘34-O1’ and ‘34-O2’) and
a second-type opening region (the third opening region; hereinafter ‘34-O3’);
the color conversion layer (the color conversion layer including first defining dam 34 and color conversion portions 35 disposed within the opening regions, FIGS. 3 and 6b-6d, [0094-0097, 0148-0150]; hereinafter ‘CCLLi’) includes
a color conversion portion (the red quantum dot conversion portion and the green quantum dot conversion portion of 35, FIGS. 3 and 6c, [0096-0097, 0149]; hereinafter ‘35-1’ and ‘35-2’) and
a filling portion (scattering particle portion 35, FIGS. 3 and 6c, [0096-0097, 0149]; hereinafter ‘35-3’);
the color conversion portion is arranged in the first-type opening region (35-1 and 35-2 are arranged in 34-O1 and 34-O2, FIGS. 3 and 6c), and
the filling portion is arranged in the second-type opening region (35-3 is arranged in 34-O3, FIGS. 3 and 6c);
the color conversion portion includes a quantum dot conversion portion or a fluorescent color conversion portion (35-1 and 35-2 containing quantum dot luminescent materials, [0097]); and
the filling portion includes a scattering particle portion or transparent glue (35-3 containing scattering particles, [0097]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Li to obtain and achieve the chip structure wherein the plurality of opening regions include a first-type opening region and a second-type opening region; the color conversion layer includes a color conversion portion and a filling portion; the color conversion portion is arranged in the first-type opening region, and the filling portion is arranged in the second-type opening region; the color conversion portion includes a quantum dot conversion portion or a fluorescent color conversion portion; and the filling portion includes a scattering particle portion or transparent glue as claimed, because the quantum dot conversion portion convert incident light into desired colors, while the scattering particle portion uniformly emits the incident light, thereby providing the respective sub-pixel with different colors and improving the display effect [0097-0098].
Regarding claim 9, Xue in view of Wu and Li teaches the chip structure according to claim 7, wherein the base substrate (Xue: sapphire substrate 11, FIG. 11) includes
a functional region (a central region of 11 orthographically overlapped by color conversion region 2 and light-emitting chip 5, FIG. 11; hereinafter ‘FR’) and
a peripheral region (a peripheral region of 11 surrounding FR and extending to the side surfaces of 11, FIG. 11; hereinafter ‘PR’) surrounding the functional region (PR surrounding FR, FIG. 11),
and an orthographic projection of the chip wafer unit on the base substrate is located in the functional region (an orthographic projection of the chip wafer unit CWF including 5 and 42 on 11 is located within FR, FIG. 11);
the body portion is located at least in the functional region (the body portion 11-B is located at least in FR, FIG. 11), and
the edge portion is located in the peripheral region (the edge portion 11-E is located in PR, FIG. 11).
Xue in view of Wu does not teach the chip structure wherein the color conversion unit further includes: an encapsulation layer covering the color filter layer, wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion.
Li teaches the chip structure wherein the color conversion unit (30, FIGS. 3 and 6a-6d) further includes:
an encapsulation layer (a quantum dot inorganic encapsulation layer 36, FIG. 3, [0105]) covering the color filter layer (36 covering CFL, FIGS. 3 and 6d, [0150]),
wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion (a peripheral portion of the orthographic projection of 36 on PI 31 being located outside the functional sub-pixel region and overlapping with the edge portion surrounding the functional sub-pixel region, FIGS. 3 and 6d).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Li to obtain and achieve the chip structure wherein the color conversion unit further includes: an encapsulation layer covering the color filter layer, wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion as claimed, because extending the encapsulation layer over the peripheral region provides continuous coverage of the color filter layer, thereby protecting the underlying color filter and color conversion structures from the external environment [0150].
Regarding claim 20, Xue in view of Wu and Li teaches the chip structure according to claim 8, wherein the base substrate (Xue: sapphire substrate 11, FIG. 11) includes
a functional region (a central region of 11 orthographically overlapped by color conversion region 2 and light-emitting chip 5, FIG. 11; hereinafter ‘FR’) and a peripheral region (a peripheral region of 11 surrounding FR and extending to the side surfaces of 11, FIG. 11; hereinafter ‘PR’) surrounding the functional region (PR surrounding FR, FIG. 11),
and an orthographic projection of the chip wafer unit on the base substrate is located in the functional region (an orthographic projection of the chip wafer unit CWF including 5 and 42 on 11 is located within FR, FIG. 11);
the body portion is located at least in the functional region (the body portion 11-B is located at least in FR, FIG. 11), and
the edge portion is located in the peripheral region (the edge portion 11-E is located in PR, FIG. 11).
Xue in view of Wu does not teach the chip structure wherein the color conversion unit further includes: an encapsulation layer covering the color filter layer, wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion.
Li teaches the chip structure wherein the color conversion unit (30, FIGS. 3 and 6a-6d) further includes:
an encapsulation layer (a quantum dot inorganic encapsulation layer 36, FIG. 3, [0105]) covering the color filter layer (36 covering CFL, FIGS. 3 and 6d, [0150]),
wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion (a peripheral portion of the orthographic projection of 36 on PI 31 being located outside the functional sub-pixel region and overlapping with the edge portion surrounding the functional sub-pixel region, FIGS. 3 and 6d).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Li to obtain and achieve the chip structure wherein the color conversion unit further includes: an encapsulation layer covering the color filter layer, wherein a portion, located in the peripheral region, of an orthographic projection of the encapsulation layer on the base substrate overlaps with the edge portion as claimed, because extending the encapsulation layer over the peripheral region provides continuous coverage of the color filter layer, thereby protecting the underlying color filter and color conversion structures from the external environment [0150].
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A) and Li (CN 113725249A) as applied to claims 1 & 7 above, and further in view of Piech et al. (US 2019/0389007; hereinafter ‘Piech’).
Regarding claim 10, Xue in view of Wu and Li teaches the chip structure according to claim 7, but does not teach the chip structure wherein a distance between a border of the black matrix and a side surface of the base substrate is e1, a size of a modified layer in a direction that is parallel to the first surface and perpendicular to the side surface is e2, and e2≤e1.
Piech teaches a chip structure (FIGS. 1-2, [0011-0012, 0036-0037]) wherein a distance between a border of the black matrix and a side surface of the base substrate is e1, a size of a modified layer in a direction that is parallel to the first surface and perpendicular to the side surface is e2, and e2≤e1 (the distance from edge 163a of black matrix layer 163 to the cutting plane defined by focal line 113 being greater than the lateral extent of the laser modified portion form the cutting plane, with transparent workpieces 161a and 161b corresponding to the claimed base substrate, FIG. 2, [0043-0044, 0049, 0052-0054]).
As taught by Piech, one of ordinary skill in the art would utilize and modify the above teaching into Xue in view of Wu and Li to obtain and achieve the chip structure wherein a distance between a border of the black matrix and a side surface of the base substrate is e1, a size of a modified layer in a direction that is parallel to the first surface and perpendicular to the side surface is e2, and e2≤e1 as claimed, because maintaining the black matrix edge outside the lateral extent of the laser modified region prevents damage to the black matrix and unwanted light leakage at the substrate edge [0040, 0044-0045].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Piech in combination with Xue in view of Wu and Li due to the above reason.
Regarding claim 12, Xue in view of Wu, Li, and Piech teaches the chip structure according to claim 10, Xue in view of Wu and Li does not teach the chip structure wherein the distance e1 between the border of the black matrix and the side surface is in a range of 10 μm to 30 μm, inclusive.
Piech teaches the chip structure wherein the distance e1 between the border of the black matrix and the side surface is in a range of 10 μm to 30 μm, inclusive (distance 219 from edge 263a of black matrix layer 263 to the cutting plane corresponds to the claimed distance e1; for 100 μm thick substrate stack embodiment, 219 is up to 15 μm because it is about 15% or less of the total thickness of the substrate stack, FIG. 15, [0046, 0133]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Piech to obtain and achieve the chip structure wherein the distance e1 between the border of the black matrix and the side surface is in a range of 10 μm to 30 μm, inclusive as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed range overlaps or lies within a range disclosed by the prior art, a prima facie case of obviousness exists. MPEP §2144.05.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A), Li (CN 113725249A), and Piech (US 2019/0389007) as applied to claims 1, 7, 10 above, and further in view of HASHIMOTO et al. (US 2016/0071767; hereinafter ‘HASHIMOTO’).
Regarding claim 11, Xue in view of Wu, Li, and Piech teaches the chip structure according to claim 10, but Xue in view of Wu, and Li does not teach the chip structure wherein the size e2 of the modified layer in the direction that is parallel to the first surface and perpendicular to the side surface is in a range of 5 μm to 10 μm, inclusive.
Piech teaches that the redial laser spot-size parameter wo,min is at least 5 µm and also discloses ranges extending up to 10 µm, including a range of 0.75 µm to 10 µm [0116].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the radial laser spot size parameter within the overlapping range of 5 μm to 10 μm, because the laser spot size was a known result-effective variable adjustable to provide a desired Rayleigh range and low beam divergence, thereby promoting uniform formation of laser induced defects through the substrate thickness [0110, 0115-0117].
Xue in view of Wu, Li, and Piech does not explicitly teach the relationship between the radial laser spot size parameter and the lateral size e2 of the resulting modified layer.
HASHIMOTO teaches that the width of a laser modified region in a direction parallel to the substrate surface substantially equals the spot diameter of the laser beam [0053].
Accordingly, when the cutting plane bisects the modified region, its one-sided lateral size e2 corresponds to Piech’s radial spot-size parameter wo,min (HASHIMOTO, [0053]; Piech, FIG. 2).
As taught by HASHIMOTO, one of ordinary skill in the art would apply the above relationship to the laser processing taught by Piech so that the one-side lateral size e2 of the modified layer corresponds to Piech’s radial laser spot size parameter wo,min, because forming the modified region with a lateral width corresponding to the laser spot diameter enables precise control of the modified region size, thereby providing the required cutting precision and cut surface flatness [0049, 0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by HASHIMOTO in combination with Xue in view of Wu, Li, and Piech due to the above reason.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A) as applied to claim 1 above, and further in view of Lee et al. (US 2021/0375833; hereinafter ‘Lee’).
Regarding claim 13, Xue in view of Wu teaches a display apparatus (Xue: [0001]), comprising a plurality of chip structures according to claim 1.
Xue in view of Wu does not teach the display apparatus comprising a driving substrate; the driving substrate being coupled to the plurality of chip structures.
Lee teaches a display apparatus (a micro LED display 500, FIGS. 1J and 5, [0066, 0099]) comprising a driving substrate (PCB 160 having a TFT structure, [0066-0067]); the driving substrate being coupled to the plurality of chip structures (the plurality of micro-LED chips R/G/B included in micro-LED array package 14 being electrically coupled to respective solder pads 161 of 160 through conductive structures 150, FIG. 1J, [0053, 0066, 0075]).
As taught by Lee, one of ordinary skill in the art would utilize and modify the above teaching into Xue in view of Wu to obtain and achieve the display apparatus comprising a driving substrate; the driving substrate being coupled to the plurality of chip structures as claimed, because the TFT driving substrate controls each corresponding pixel and supplies and maintains a desired driving voltage, [0067].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Lee in combination with Xue in view of Wu due to the above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A) as applied to claim 14 above, and further in view of Kobayashi (US 2008/0124898).
Regarding claim 15, Xue in view of Wu teaches the method according to claim 14, but does not teach the method wherein in the step of sequentially applying the laser to the plurality of focuses inside the base substrate motherboard for cutting, the base substrate motherboard is cut from a side of the color conversion substrate of the coupling structure away from the initial wafer.
Kobayashi teaches a method [0006] wherein in the step of sequentially applying the laser to the plurality of focuses inside the base substrate motherboard for cutting (sequentially forming a plurality of deteriorated layers inside a wafer 10, FIGS. 10-11, [0002, 0073, 0075]), the base substrate motherboard is cut from a side of the color conversion substrate of the coupling structure away from the initial wafer (first forming a first deteriorated layer 130 near rear surface 10b and subsequently forming a second deteriorated layer 140 at a position closer to front surface 10a than 130, FIG. 12).
As taught by Kobayashi, one of ordinary skill in the art would utilize and modify the above teaching into Xue in view of Wu to obtain and achieve the method wherein in the step of sequentially applying the laser to the plurality of focuses inside the base substrate motherboard for cutting, the base substrate motherboard is cut from a side of the color conversion substrate of the coupling structure away from the initial wafer as claimed, because this processing sequence efficiently forms deteriorated layers having a required thickness while avoiding damage to devices located on the device side surface [0014, 0066].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kobayashi in combination with Xue in view of Wu due to the above reason.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xue (CN 114709319A) in view of Wu (CN 107538136A) as applied to claim 14 above, and further in view of PRIEWASSER et al. (US 2020/0312717; hereinafter ‘PRIEWASSER’).
Regarding claim 19, Xue in view of Wu teaches the method according to claim 14, but does not teach the method wherein a distance between any two adjacent chip structures is in a range of 20 μm to 50 μm, inclusive.
PRIEWASSER teaches a method [0009] wherein a distance between any two adjacent chip structures is in a range of 20 μm to 50 μm, inclusive (the width of a division line between adjacent devices is in a range of 10-50 μm, [0004, 0025].
As taught by PRIEWASSER, one of ordinary skill in the art would utilize and modify the above teaching into Xue in view of Wu to obtain and achieve the method wherein a distance between any two adjacent chip structures is in a range of 20 μm to 50 μm, inclusive as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by PRIEWASSER in combination with Xue in view of Wu due to the above reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that JAMES et al. (US 2018/0233410), Miccoli et al. (US 2012/0211748), and Kirihara (US 0218/0309018) as a laser-based method for the singulation of integrated circuit die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/14/26
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