Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 20190278145 A1).
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CLAIM 1. Tanaka teaches a display panel, comprising a display area and a fan-out area located in the display area, wherein the display panel further comprises:
a base substrate (Tanaka Fig. 15);
a plurality of data lines 12 located in the display area, wherein orthographic projections of the data lines on the base substrate are arranged at intervals along a first direction (Y) and extend along a second direction (X), the first direction (Y) intersecting the second direction (X) (Tanaka Fig. 15);
a plurality of first data fan-out lines 120P located in the fan-out area, wherein orthographic projections of the first data fan-out lines on the base substrate are arranged at intervals along the second direction (X) and extend along the first direction (Y), and the first data fan-out line is arranged corresponding to and connected with a respective data line (Tanaka Fig. 15);
a plurality of second data fan-out lines 120P located in the fan-out area, wherein orthographic projections of the second data fan-out lines on the base substrate are arranged at intervals along the first direction (Y) and extend along the second direction (X), and the second data fan-out line is arranged corresponding to and connected with a respective first data fan-out line (Tanaka Fig. 2B).
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CLAIM 2. Tanaka teaches a display panel according to claim 1, wherein the display panel further comprises: a plurality of first signal lines located in the display area, wherein orthographic projections of the first signal lines on the base substrate extend along the first direction (Y) and are arranged at intervals along the second direction (X), the plurality of first signal lines comprises a first signal sub-line, and at least a partial structure of the first signal sub-line is used to form the first data fan-out line (Tanaka figs. 2B & 15);
a plurality of second signal lines located in the display area and arranged on a different conductive layer than the first signal lines, wherein orthographic projections of the second signal lines on the base substrate extend along the second direction (X) and are arranged at intervals along the first direction (Y), the plurality of second signal lines comprises a second signal sub-line, and at least a partial structure of the second signal sub-line is used to form the second data fan-out line (Tanaka figs. 2B & 15).
CLAIM 9. Tanaka teaches a display panel according to claim 2, wherein the plurality of first signal lines is located on the same conductive layer, and the plurality of second signal lines is located on the same conductive layer; and the conductive layer where the second signal line is located is arranged on a side away from the base substrate of the conductive layer where the first signal line is located (Tanaka figs. 2B & 15).
CLAIM 11. (original) The display panel according to claim 2, wherein the first signal line comprises a plurality of first via contact portions and a first extension portion, wherein orthographic projections of the plurality of first via contact portions on the base substrate are arranged at intervals along the first direction (Y), the first extension portion is connected to the first via contact portion, and an orthographic projection of the first via contact portion on the base substrate has a dimension in the second direction (X) being greater than a dimension in the second direction (X) of an orthographic projection of the first extension portion on the base substrate (Tanaka figs. 2B & 15).;
the second signal line comprises a plurality of second via contact portions and a second extension portion, wherein orthographic projections of the plurality of second via contact portions on the base substrate are arranged at intervals along the second direction (X), the second extension portion is connected to the second via contact portion, and an orthographic projection of the second via contact portion on the base substrate has a dimension in the first direction (Y) being larger than a dimension in the first direction (Y) of an orthographic projection of the second extension portion on the base substrate; and the first via contact portion is arranged corresponding to a respective second via contact portion, the orthographic projection of the first via contact portion on the base substrate at least partially overlaps with the orthographic projection on the base substrate of the respective second via contact portion, and at least some of the first via contact portions are connected to the respective second via contact portions through via holes (Tanaka figs. 2B & 15)..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6, 8, 19-25 & 27-29 & 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2019/0278145 A1) in view of Yan et al. (CN 114695491 A) .
CLAIM 3. Tanaka et al. (FIGS. 1–2B, ¶28, 41) discloses the display panel according to claim 2, wherein the display panel comprises a base substrate, a plurality of first signal lines, and a plurality of second signal lines.
Tanaka et al. is silent upon explicitly disclosing that the minimum distance in the second direction (X) between orthographic projections of two adjacent first signal lines on the base substrate is S1, and the maximum distance in the second direction (X) between orthographic projections of two adjacent first signal lines on the base substrate is S2, where (S2-S1)/S1 is greater than or equal to 0 and less than or equal to 0.2; and/or the minimum distance in the first direction (Y) between orthographic projections of two adjacent second signal lines on the base substrate is S3, and the maximum distance in the first direction (Y) between orthographic projections of two adjacent second signal lines on the base substrate is S4, where (S4-S3)/S3 is greater than or equal to 0 and less than or equal to 0.2.
However, Yan (FIGS. 1, 9, 16; Detailed Description) teaches arraying sub-pixel control lines and routing signal lines across active matrix display panels with substantially uniform spatial pitch and spacing tolerance. It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine the teachings of Tanaka et al. and Yan to set signal line spacing across the X and Y directions within a uniform variation ratio (\le 0.2) in order to ensure uniform parasitic capacitance, consistent signal propagation delays, and reliable fabrication tolerances across the panel array.
CLAIM 4. Tanaka et al. (FIGS. 1–2B, ¶28, 41) in view of Yan discloses the display panel according to claim 2, including data lines, fan-out lines, and fan-out regions.
Tanaka et al. is silent upon explicitly disclosing that the first signal sub-line further comprises a first simulation line spaced apart from the first data fan-out line, and the second signal sub-line further comprises a second simulation line spaced apart from the second data fan-out line; the fan-out area comprises a first fan-out area and a second fan-out area, the first data fan-out line is located in the first fan-out area, and the second data fan-out line is located in the second fan-out area; the plurality of first signal lines further comprises a third simulation line, and the third simulation line is located in the display area outside the first fan-out area; the plurality of second signal lines further comprises a fourth simulation line, and the fourth simulation line is located in the display area outside the second fan-out area.
However, Yan (FIGS. 1, 8, 16; Detailed Description) teaches incorporating dummy/simulation signal lines (e.g., dummy1, dummy2) situated alongside active signal and fan-out lines within peripheral and display regions. It would have been obvious to a person having ordinary skill in the art at the time of the invention to integrate these third and fourth simulation lines outside the primary fan-out areas to balance RC loading, equalize wiring density, and prevent optical load discrepancies across the active display boundary.
CLAIM 5. Tanaka et al. (FIGS. 1–2B, 15; ¶41, 44) in view of Yan discloses the display panel according to claim 4, further comprising a pixel driving circuit, a light-emitting unit, and a common electrode layer connected to light-emitting units.
Tanaka et al. is silent upon explicitly disclosing that the first simulation line, the second simulation line, the third simulation line, and the fourth simulation line are connected to the common electrode layer.
However, Yan (FIGS. 1, 16; Detailed Description) in view of Yan discloses grounding or tying dummy/simulation wiring to a common power supply voltage or common electrode reference (e.g., VSS/VDD/common ground). It would have been obvious to a person having ordinary skill in the art at the time of the invention to connect all four simulation lines to the common electrode layer to shield adjacent active data lines from crosstalk and prevent floating metal potential instability.
CLAIM 6. Tanaka et al. (FIGS. 2A, 2B; ¶47–48) in view of Yan discloses the display panel according to claim 4, wherein signal routing lines cross and interconnect via through holes.
Tanaka et al. is silent upon explicitly disclosing that the first simulation line is connected through a via hole to the fourth simulation line that intersects an orthographic projection of the first simulation line on the base substrate; and the third simulation line is connected through via holes to the second simulation line and the fourth simulation line that intersect an orthographic projection of the third simulation line on the base substrate.
However, Yan (FIGS. 1, 8, 16; Detailed Description) teaches routing intersecting dummy/simulation lines across different conductive layers and connecting them together through via contact holes. It would have been obvious to a person having ordinary skill in the art at the time of the invention to interconnect intersecting simulation lines through via holes to form a unified, low-impedance shielding grid across the display panel.
CLAIM 8. Tanaka et al. (FIGS. 2A, 2B) in view of Yan discloses the display panel according to claim 4, wherein the fan-out region comprises sub-areas on both sides of the fan-out routing area.
Tanaka et al. is silent upon explicitly disclosing that the first fan-out area comprises a first fan-out sub-area and a second fan-out sub-area, the first fan-out sub-area and the second fan-out sub-area being located on both sides in the first direction (Y) of the second fan-out area; the plurality of second signal lines further comprises at least one fifth simulation line, wherein a partial structure of the fifth simulation line is located in the second fan-out area, and the fifth simulation line is connected through via holes respectively to the first simulation line and the third simulation line that intersect an orthographic projection of the fifth simulation line on the base substrate.
However, Yan (FIGS. 8, 16; Detailed Description) teaches distributing auxiliary dummy lines across fan-out sub-regions and tying them via contact holes to intersecting primary simulation traces. It would have been obvious to a person having ordinary skill in the art at the time of the invention to route a fifth simulation line through the second fan-out area and tie it to the first and third simulation lines to ensure consistent metal density and uniform RC balance across divided fan-out zones.
CLAIM 19. Tanaka et al. (FIGS. 2A, 2B; ¶48–49) in view of Yan discloses the display panel according to claim 11, wherein the data line comprises extension portions routed in the frame region.
Tanaka et al. is silent upon explicitly disclosing that the data line, the orthographic projection of which on the base substrate is located on adjacent sides of the second signal line, comprises a third extension portion, a fourth extension portion, and a fifth extension portion, the fourth extension portion being connected between the third extension portion and the fifth extension portion, and at least partial structures of the second via contact portion and the fourth extension portion are oppositely disposed in the first direction (Y); dimensions in the first direction (Y) of an orthographic projection of the fourth extension portion on the base substrate and an orthographic projection of the second extension portion on the base substrate are larger than dimensions in the first direction (Y) of an orthographic projection of the third extension portion on the base substrate and an orthographic projection of the second extension portion on the base substrate; dimensions in the first direction (Y) of an orthographic projection of the fourth extension portion on the base substrate and an orthographic projection of the second extension portion on the base substrate are larger than dimensions in the first direction (Y) of an orthographic projection of the fifth extension portion on the base substrate and an orthographic projection of the second extension portion on the base substrate.
However, Yan (FIGS. 9, 16; Detailed Description) teaches shaping data line routing extensions with widened bridge portions located adjacent to contact via structures. It would have been obvious to a person having ordinary skill in the art at the time of the invention to configure the fourth extension portion with larger Y-direction dimensions relative to the third and fifth extension portions to lower contact resistance at via connections and prevent line breakage during high-density layout bending.
CLAIM 20. Tanaka et al. (FIGS. 1–2B, 15; ¶32, 44) in view of Yan discloses the display panel according to claim 4, comprising a pixel driving circuit, a light-emitting unit, and an electrode layer comprising electrode portions forming first electrodes.
Tanaka et al. is silent upon explicitly disclosing that an orthographic projection of a notch between the first data fan-out line and the first simulation line on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate; and/or an orthographic projection of a notch between the second data fan-out line and the second simulation line on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate.
However, Yan (FIGS. 15, 16; Detailed Description) teaches arranging pixel electrode patterns to avoid overlapping routing gaps/notches between adjacent fan-out and simulation lines. It would have been obvious to a person having ordinary skill in the art at the time of the invention to offset the electrode portion relative to line notches to reduce unwanted parasitic coupling capacitance between fan-out signal lines and display pixel electrodes.
Claim 21. Tanaka et al. (FIGS. 2A, 15; ¶44) discloses the display panel according to claim 11, comprising a pixel driving circuit, a light-emitting unit, and an electrode layer with electrode portions.
Tanaka et al. is silent upon explicitly disclosing that an orthographic projection of the first via contact portion on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate; and an orthographic projection of the second via contact portion on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate.
However, Yan (FIGS. 15, 16; Detailed Description) teaches staggering via contact positions away from the pixel electrode boundaries. It would have been obvious to a person having ordinary skill in the art at the time of the invention to locate the first and second via contact projections outside the footprint of the pixel electrode portion to avoid topography-induced step coverage defects and prevent capacitive noise from coupling directly into light-emitting anodes.
CLAIM 22. Tanaka (Figs 1-2A, 2b, 15, ¶28, 41, 44-45) in view of Yan discloses the display panel according to claim 2, wherein the display panel further comprises a plurality of pixel driving circuits and a plurality of light-emitting units, the plurality of pixel driving circuits being arranged in an array along the first direction (Y) and the second direction (X), and the pixel driving circuit being connected to a first electrode of the light-emitting unit; the pixel driving circuit comprises a driving transistor, a sixth transistor, and a seventh transistor; and the display panel further comprises: a first active layer located on a side of the base substrate, wherein the first active layer comprises a sixth active portion and a seventh active portion, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; and a first gate layer located on a side of the first active layer away from the base substrate, wherein the first gate layer comprises an enable signal line and a second reset signal line (Tanaka, Figs 1-2A, 2b, 15, ¶28, 41, 44-45 ).
Tanaka may be silent upon explicitly disclosing that "a first terminal of the sixth transistor is connected to a second terminal of the driving transistor, a second terminal of the sixth transistor is connected to the first electrode of the light-emitting unit; a first terminal of the seventh transistor is connected to a second initial signal line, and a second terminal of the seventh transistor is connected to the first electrode of the light-emitting unit; and that an orthographic projection of the enable signal line on the base substrate extends along the first direction (Y) and covers an orthographic projection of the sixth active portion on the base substrate, and an orthographic projection of the second reset signal line on the base substrate extends along the first direction (Y) and covers an orthographic projection of the seventh active portion on the base substrate, wherein the first direction (Y) is a row direction, and an orthographic projection of the first signal line on the base substrate is located between orthographic projections on the base substrate of the enable signal line and the second reset signal line in the same row of pixel driving circuits.
However, configuring the specific terminal interconnections and routing control lines to overlap their respective active channel regions as claimed constitutes a conventional 7-transistor sub-pixel circuit arrangement. It would have been obvious to a person having ordinary skill in the art at the time of the invention to connect the sixth and seventh transistor terminals and align the enable and reset lines over their respective channel regions, as selecting well-known sub-pixel control topologies and routing gate lines accordingly is a matter of routine layout optimization in display panel design.
CLAIM 23. Tanaka (Figs 1-2A, 2b, 15, ¶28, 41, 44-45) in view of Yan discloses the display panel according to claim 11, wherein the display panel further comprises a plurality of pixel driving circuits and a plurality of light-emitting units, the plurality of pixel driving circuits being arranged in an array along the first direction (Y) and the second direction (X), and the pixel driving circuit being connected to a first electrode of the light-emitting unit; the pixel driving circuit comprises a driving transistor, a sixth transistor, and a first transistor; and the display panel further comprises: a first gate layer located on a side of the base substrate, wherein the first gate layer comprises an enable signal line, and a partial structure of the enable signal line is used to form a gate of the sixth transistor; and a second gate layer located on a side of the first gate layer away from the base substrate (Tanaka, Figs 1-2A, 2b, 15, ¶28, 41, 44-45 ).
Tanaka may be silent upon explicitly disclosing that a first terminal of the sixth transistor is connected to a second terminal of the driving transistor, a second terminal of the sixth transistor is connected to the first electrode of the light-emitting unit; a first terminal of the first transistor is connected to a first initial signal line, and a second terminal of the first transistor is connected to a gate of the driving transistor; and that an orthographic projection of a first extension portion in the first signal line is located between an orthographic projection on the base substrate of the first initial signal line in the same row of pixel driving circuits and an orthographic projection on the base substrate of the enable signal line in an adjacent next row of pixel driving circuits.
However, establishing these specific transistor terminal connections and positioning signal lines relative to adjacent row control lines represent standard sub-pixel circuit layout practices. It would have been obvious to a person having ordinary skill in the art at the time of the invention to utilize these specific terminal connections and line arrangements to provide predictable switching, initialization, and signal distribution across adjacent pixel rows.
CLAIM 24 Tanaka (Figs 1-2A, 2b, 15) in view of Yan discloses the display panel according to claim 2, wherein the display panel comprises a plurality of repetition units arranged in an array along the first direction (Y) and the second direction (X).
Tanaka may be silent upon explicitly disclosing that the repetition unit comprises n rows and m columns of repetition sub-units, n and m being positive integers greater than or equal to 1; the repetition sub-unit comprises two pixel driving circuits arranged adjacently in the first direction (Y), the two pixel driving circuits in the same repetition sub-unit being arranged in mirror symmetry; a plurality of the repetition units arranged along the second direction (X) form a column of repetition units, and one of the second signal lines is provided correspondingly between two adjacent columns of repetition units in the first direction (Y); and a plurality of the repetition units arranged along the first direction (Y) form a row of repetition units, and each row of repetition units is provided with a respective first signal line.
However, grouping pixel circuits into repeating sub-units arranged in rows and columns with mirror symmetry and routing signal lines between adjacent columns is conventional in the art. It would have been obvious to a person having ordinary skill in the art at the time of the invention to organize the pixel array into symmetrical repeating units and route signal lines between adjacent unit columns in order to maximize layout density, simplify mask fabrication, and maintain uniform signal delivery across the panel.
CLAIM 25 Tanaka (Figs 1-2A, 2b, 15, ¶28, 41, 44-45) in view of Yan discloses the display panel according to claim 24, wherein the display panel further comprises a light-emitting unit, the pixel driving circuit being connected to a first electrode of the light-emitting unit; the display panel further comprises an electrode layer, the electrode layer comprising a plurality of electrode portions, and the electrode portion being used to form the first electrode of the light-emitting unit.
Tanaka may be silent upon explicitly disclosing that an orthographic projections of two adjacent repetition sub-units in the first direction (Y), orthographic projections of two adjacent data lines on the base substrate intersect an orthographic projection of the same electrode portion on the base substrate, and are located on both sides of an orthographic projection of the second signal line on the base substrate.
However, configuring electrode layer portions to span adjacent sub-units while allowing adjacent data lines to intersect on opposite sides of a second signal line represents a routine layout variation. It would have been obvious to a person having ordinary skill in the art at the time of the invention to position electrode portions over adjacent pixel sub-units to facilitate efficient power distribution and optimize pixel layout geometry.
CLAIM 27. Tanaka et al. (FIGS. 1–2B, ¶28, 41]) in view of Yan discloses the display panel according to claim 24 (n ≥2), comprising rows of pixel driving circuits, driving transistors, sixth transistors, and seventh transistors.
Tanaka et al. is silent upon explicitly disclosing that the first terminal of the sixth transistor is connected to a second terminal of the driving transistor, a second terminal of the sixth transistor is connected to the first electrode of the light-emitting unit, and a gate of the sixth transistor is connected to an enable signal line; a first terminal of the seventh transistor is connected to a second initial signal line, a second terminal of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to a second reset signal line; the same row of repetition units comprises a first row of pixel driving circuits and a second row of pixel driving circuits; in the first row of pixel driving circuits, the minimum distance in the second direction (X) between an orthographic projection of the enable signal line and the second reset signal line is L3; in the second row of pixel driving circuits, the minimum distance in the second direction (X) between an orthographic projection of the enable signal line and the second reset signal line is L4; and L3 is larger than L4.
However, Yan (FIGS. 1,2, 9, 16; Detailed Description) teaches configuring sub-pixel control lines (EM, Re) across adjacent rows with varied inter-line spacing distances (L3 > L4). It would have been obvious to a person having ordinary skill in the art at the time of the invention to adopt different signal line spacings (L3 > L4) across adjacent rows to accommodate asymmetrical layout routing, balance signal propagation delays, and optimize pixel density within repeating sub-unit rows.
CLAIM 28 Tanaka (Figs 1-2A, 2b, 15, ¶28, 41, 44-45) in view of Yan discloses the display panel according to claim 1, wherein the display panel comprises a pixel driving circuit and a light-emitting unit, the pixel driving circuit comprising a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor(Tanaka, Figs 1-2A, 2b, 15, ¶28, 41, 44-45 ).
Tanaka may be silent upon explicitly disclosing that the first transistor has a first terminal connected to a first initial signal line and a second terminal connected to a gate of the driving transistor; the second transistor has a first terminal connected to a gate of the driving transistor and a second terminal connected to a second terminal of the driving transistor; the fourth transistor has a first terminal connected to the data line and a second terminal connected to a first terminal of the driving transistor; the fifth transistor has a first terminal connected to a power line and a second terminal connected to a first terminal of the driving transistor; the sixth transistor has a first terminal connected to a second terminal of the driving transistor and a second terminal connected to a first electrode of the light-emitting unit; the seventh transistor has a first terminal connected to a second initial signal line and a second terminal connected to the first electrode of the light-emitting unit; and the capacitor has a first electrode connected to a gate of the driving transistor and a second electrode connected to the power line.
However, the specific terminal interconnections recited define a standard 7-transistor, 1-capacitor (7T1C) sub-pixel driving circuit. It would have been obvious to a person having ordinary skill in the art at the time of the invention to implement this specific 7T1C interconnection scheme in order to achieve predictable threshold voltage compensation, signal programming, and light-emission control, as selecting standard 7T1C sub-pixel topologies is a matter of conventional circuit choice.
CLAIM 29 Tanaka (Figs 1-2A, 2b, 15, ¶28, 41, 44-45) in view of Yan discloses the display panel according to claim 28, wherein the display panel further comprises: a first active layer located on a side of the base substrate, and a first gate layer located on a side of the first active layer away from the base substrate, wherein the first gate layer comprises a first gate line, an enable signal line, a second reset signal line, and a first conductive portion (Tanaka, Figs 1-2A, 2b, 15, ¶28, 41, 44-45 ).
Tanaka may be silent upon explicitly disclosing that the first active layer comprises a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion, the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fifth transistor, the fifth active portion is used to form a channel region of the fourth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor;" and that "an orthographic projection of the first gate line on the base substrate extends along the first direction (Y) and covers an orthographic projection of the fourth active portion on the base substrate, an orthographic projection of the enable signal line on the base substrate extends along the first direction (Y) and covers orthographic projections of the fifth active portion and the sixth active portion on the base substrate, an orthographic projection of the second reset signal line on the base substrate extends along the first direction (Y) and covers an orthographic projection of the seventh active portion on the base substrate.
However, patterning the active layer into specific channel portions and extending gate signal lines across their corresponding channel regions represent standard semiconductor layout practices. It would have been obvious to a person having ordinary skill in the art at the time of the invention to structure the active layer channel regions and overlap the gate control lines accordingly to form the functional switching and driving transistors of the circuit of claim 28.
CLAIM 33. Tanaka et al. (FIGS. 1–2B, ¶28, 41) in view of Yan discloses a display apparatus comprising a display panel, a display area, a fan-out area located in the display area, a base substrate, data lines in the display area extending along a second direction (X) and arranged along a first direction (Y), first data fan-out lines located in the fan-out area extending along the first direction (Y) connected to respective data lines, and second data fan-out lines extending along the second direction (X) connected to respective first data fan-out lines.
Tanaka et al. is silent upon explicitly disclosing the specific combination of simulation lines and sub-pixel routing layout.
However, Yan (FIGS. 1, 8, 16; Detailed Description) teaches incorporating dummy simulation wiring alongside fan-out networks and arranging data/fan-out lines in systematic geometric steps. It would have been obvious to a person having ordinary skill in the art at the time of the invention to combine Tanaka et al. and CN 114695491 A to organize the data lines, fan-out lines, and simulation lines as claimed in order to provide uniform display impedance, reduce signal line interference, and achieve narrow frame borders.
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/24/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
Prosecution Insights