DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013 is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This action is a first action on the merits in response to the application filed on 05/24/2024.
Status of Claims
Claims 1-13 filed on 05/24/2024 are currently pending and have been examined in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claim 4 objected to as being dependent upon rejected base claims, but it appears it would be distinguished from the prior art references cited by the Examiner if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claims is directed to signals per se. Applicant has claimed a storage medium and Applicant's specification fails to narrowly define the storage medium to exclude transitory propagating signals. The broadest reasonable interpretation of a claim drawn to a storage medium includes transitory propagating signals per se in view of the ordinary and customary meaning of machine-readable medium device, which are non-statutory subject matter. A storage medium claim can legally encompass transitory propagating signals if the broadest reasonable interpretation of the claim language fails to exclude them, which makes the claim invalid under 35 U.S.C. § 101. As a result, this claim must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007). In order to overcome this rejection under 35 U.S.C. 101.
In the present case, the applicant’s specification paragraph [0020] does not exclude transitory propagating signals.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-13 are rejected under 35 U.S.C. 103 as being un-patentable over Hsieh (US 20210191723 A1) in view of Bertran et al. (US 20170147058 A1).
Regarding claim 1. Hsieh teaches A generation method for a chip internal voltage prediction model, comprising: obtaining a load data set and a relevant index data set of a chip respectively, [Hsieh, claim 1 , Hsieh teaches “a voltage detection circuit, configured to detect a voltage of the processor to output a voltage value; and a neural network circuit, comprising a plurality of functions and a plurality of parameters, wherein the neural network circuit is configured to operate in a training mode or a prediction mode”]
Hsieh does not specifically teach, however, Bertran teaches wherein the load data set comprises load data of the chip at each sampling cycle and a sampling cycle ordinal number corresponding to the load data, and the relevant index data set comprises characterization data characterizing a chip internal voltage at the each sampling cycle and a sampling cycle ordinal number corresponding to the characterization data; calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training [Bertran, para. 0008, Bertran teaches “A method for executing an application includes predicting a minimum operational voltage for a next epoch of an application, using a processor, based on performance counters collected in a previous epoch of the application”, para. 0024 teaches “The microprocessor 106 records performance counters 112 for each epoch and the firmware 114 accesses those performance counters at the end of the respective epoch. The performance counters 112 are hardware features that include a set of counters recording microprocessor activities such as, e.g., instructions per cycle and number of cache misses” wherein the respective epoch is equivalent to sampling cycle. Further, claim 7 teaches “re-executing the next epoch using a nominal safe voltage if an error is detected from an undervoltage condition” wherein re-executing the next epoch using a nominal safe is equivalent to calibrating]
Hsieh teaches the chip can predict whether the processor may operate at a voltage less than a rated voltage and take a corresponding measure, to ensure normal operation of the chip and Bertran teaches safely reducing wasted energy and, more particularly, to safely optimizing chip operating voltage. The two references are in the same field of endeavor as the claimed invention and solving the same problem of improving accuracy of sampling data. It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine utilizing the chip internal voltage prediction of Hsieh with cycle sampling and calibration of Bertran since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing chip voltage data sampling.
Regarding claims 2-3. Hsieh in view of Bertran teaches all of the limitations of claim 1 as above. Hsieh does not specifically teach, however, Bertran teaches wherein the load data comprises instruction data and/or cache data, the instruction data is a number of each type of instructions in an instruction life cycle of the chip, and the cache data is a number of reads and writes in progress in a cache of the chip. Wherein the characterization data is power monitoring data and/or power consumption data [Bertran, para. 0024 teaches “Firmware layer 104 operates in units of “epochs,” which may be a certain number of processor cycles, a number of executed instructions, loop counts, or function counts. The firmware layer 104 includes an offline trained Vmin prediction model 110 to control the voltage 114 of the microprocessor 106. The microprocessor 106 records performance counters 112 for each epoch and the firmware 114 accesses those performance counters at the end of the respective epoch. The performance counters 112 are hardware features that include a set of counters recording microprocessor activities such as, e.g., instructions per cycle and number of cache misses”]
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine utilizing the chip internal voltage prediction of Hsieh with cycle sampling and calibration of Bertran since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing chip voltage data sampling.
The additional limitations in claims 2-3 do not serve a specific technical purpose and cannot contribute to the invention's technical character. Claims 2-3 do not produce any technical effect beyond the provision of their computer implementation. Features that do not contribute to an invention's technical character cannot support the presence of an inventive step. For these reasons, when confronted with the objective technical problem, the skilled person would implement the subject matter of claims 2-3 in the context of closest prior art Hsieh and arrive at the subject matter of claims 2-3 without exercising any inventive skill.
Regarding claim 4. (Currently Amended) The generation method for the chip internal voltage prediction model according to claim 1, wherein in calibrating the relevant index data set according to the calibration cycle number and obtaining the calibrated relevant index data set, a calculation method for the calibration cycle number comprises: recording a sampling cycle ordinal number T1 corresponding to the load data reaching a maximum value of the load data, and a sampling cycle ordinal number T2 corresponding to the characterization data reaching a maximum value of the characterization data, in a process of gradually increasing a computational load of the chip to a maximum value and maintaining a state of the maximum value; and taking a difference between the sampling cycle ordinal number T1 corresponding to the load data reaching the maximum value of the load data and the sampling cycle ordinal number T2 corresponding to the characterization data reaching the maximum value of the characterization data as the calibration cycle number.
Regarding claims 5-6. Hsieh in view of Bertran teaches all of the limitations of claim 1 as above. Hsieh does not specifically teach, however, Bertran teaches wherein calibrating the relevant index data set according to the calibration cycle number comprises: reducing the sampling cycle ordinal number corresponding to the characterization data in the relevant index data set by the calibration cycle number. Wherein the sampling cycle is a clock cycle of the chip [Bertran, para. 0024 teaches “Firmware layer 104 operates in units of “epochs,” which may be a certain number of processor cycles, a number of executed instructions, loop counts, or function counts. The firmware layer 104 includes an offline trained Vmin prediction model 110 to control the voltage 114 of the microprocessor 106. The microprocessor 106 records performance counters 112 for each epoch and the firmware 114 accesses those performance counters at the end of the respective epoch. The performance counters 112 are hardware features that include a set of counters recording microprocessor activities such as, e.g., instructions per cycle and number of cache misses]
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine utilizing the chip internal voltage prediction of Hsieh with cycle sampling and calibration of Bertran since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing chip voltage data sampling.
The additional limitations in claims 5-6 do not serve a specific technical purpose and cannot contribute to the invention's technical character. Claims 5-6 do not produce any technical effect beyond the provision of their computer implementation. Features that do not contribute to an invention's technical character cannot support the presence of an inventive step. For these reasons, when confronted with the objective technical problem, the skilled person would implement the subject matter of claims 5-6 in the context of closest prior art Hsieh and arrive at the subject matter of claims 5-6 without exercising any inventive skill.
Regarding claim 7, the claim recites analogous limitations to claim 1 above, and is therefore rejected on the same premise. Claim 1 is a method claim while claim 7 is directed to an apparatus which is anticipated by Hseih claim 1.
Regarding claims 8 and 10, the claims recite analogous limitations to claim 1 above, and are therefore rejected on the same premise. Claim 1 is a method claim while claim 8 is directed to a method and claim 10 is directed to an apparatus requiring “obtaining real-time load data of a chip; and obtaining prediction data of the chip internal voltage using a chip internal voltage prediction model” which is anticipated by Hseih Abstract “The control circuit is configured to read and execute an instruction. The voltage detection circuit is configured to detect a voltage of the processor to output a voltage value”.
Regarding claim 9. Hsieh in view of Bertran teaches all of the limitations of claim 8 as above. Hsieh does not specifically teach, however, Bertran teaches wherein the real-time load data comprises instruction data and/or cache data, the instruction data is a number of each type of instructions in an instruction life cycle of the chip, and the cache data is a number of reads and writes in progress in a cache of the chip [Bertran, para. 0024 teaches “The microprocessor 106 records performance counters 112 for each epoch and the firmware 114 accesses those performance counters at the end of the respective epoch. The performance counters 112 are hardware features that include a set of counters recording microprocessor activities such as, e.g., instructions per cycle and number of cache misses”]
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify/combine utilizing the chip internal voltage prediction of Hsieh with cycle sampling and calibration of Bertran since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, with the predictable results of optimizing chip voltage data sampling.
The additional limitations in the claim do not serve a specific technical purpose and cannot contribute to the invention's technical character. Features that do not contribute to an invention's technical character cannot support the presence of an inventive step. For these reasons, when confronted with the objective technical problem, the skilled person would implement the additional features of claim 9 in the context of closest prior art Hsieh and arrive at the subject matter of claim 9 without exercising any inventive skill.
Regarding claim 11, the claim recites analogous limitations to claim 1 above, and is therefore rejected on the same premise. Claim 1 is a method claim while claim 11 is directed to a storage medium which is anticipated by Hseih claim 1.
Regarding claim 12, the claim recites analogous limitations to claim 1 above, and is therefore rejected on the same premise. Claim 1 is a method claim while claim 12 is directed to an electronic device which is anticipated by Hseih Abstract (a chip).
Regarding claim 13, the claim recites analogous limitations to claim 1 above, and is therefore rejected on the same premise. Claim 1 is a method claim while claim 13 is directed to a Chip which is anticipated by Hseih Abstract.
Conclusion
The following prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Hebert et al. (US 20240095430 A1). Hebert teaches receiving, by a hardware design generation circuit, a plurality of input signals of a software workload on a processing unit; training a power prediction model based on a toggling of the input signals accumulated over a training interval range; determining, by the hardware design generation circuit, a plurality of prediction proxies and respective weightings for the plurality of prediction proxies based at least partially on the trained power prediction model; and generating an updated circuit design of the processing unit based on the power output.
Any inquiry concerning this communication from the examiner should be directed to Abdallah El-Hagehassan whose contact information is (571) 272-0819 and Abdallah.el-hagehassan@uspto.gov The examiner can normally be reached on Monday- Friday 8 am to 5 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutao Wu can be reached on (571) 272-6045. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-3734.
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/ABDALLAH A EL-HAGE HASSAN/
Primary Examiner, Art Unit 3623
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