CTNF 18/713,565 CTNF 91783 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 5/24/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-2, 12-14, 18 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Im et al. US 2019/0115513 . Re Claim1 , Im teaches a display device (fig1) having a semiconductor light emitting device (40, fig2 and 3A, [65]), comprising: a substrate (100, fig4B, [79]); a first assembly wiring (21, fig2 and 4B, [58]) and a second assembly wiring (22, fig2 and 4B, [58]) arranged to be spaced apart from each other on the substrate; a planarization layer (30, fig4B, [81]) disposed on the first assembly wiring (21, fig2 and 4B, [58]) and the second assembly wiring (22, fig2 and 4B, [58]) and having an opening (space between 30, fig2 and 4B, [81]) overlapping the first assembly wiring and the second assembly wiring (fig2 and 4B); and a light emitting device (40, fig2 and 3A, [65]) disposed inside the opening and comprising a first electrode (410 or 420, fig3A, [65]) electrically connected to the first assembly wiring (one end with 410 or 420 connected to 21, fig3A and 4B, [65]), wherein the opening comprises a main opening (opening between 31 and 32, fig4B, [81]) and one or more auxiliary openings (space between 30 and 31 and space between 30 and 32, fig2 and 4B) connected to the main opening (opening between 31 and 32, fig4B, [81]) and smaller than the main opening (space between 30 and 31 or 30 and 32 smaller than main opening between 30, fig2 and 4B). Re Claim 2 , Im teaches the display device according to claim 1, wherein the first assembly wiring (21, fig 4B, [58]) is disposed above the second assembly wiring (22, fig4B, [58]), wherein the first electrode (410 or 420, fig3A, [65]) is in contact with the first assembly wiring (one end with 410 or 420 connected to 21, fig3A and 4B, [65]), and wherein the auxiliary opening (space between 30 and 31 and space between 30 and 32, fig2 and 4B) is configured to overlap the first assembly wiring (21, fig4B). Re Claim 12 , Im teaches a display device (fig1) having a semiconductor light emitting device (40, fig2 and 3A, [65]), comprising: a substrate (100, fig4B, [79]) with a plurality of a sub pixels (PX, fig1 and 2, [55]) defined; a plurality of a first assembly wirings (21, fig2 and 4B, [58]) arranged along the plurality of sub pixels arranged on a same line among the plurality of sub pixels (along DL, fig1); a plurality of a second assembly wirings (22, fig2 and 4B, [58]) arranged along the plurality of sub pixels arranged on a same line among the plurality of sub pixels (along DL, fig1) and arranged adjacent to each of the first assembly wirings (21, fig2 and 4B, [58]); a planarization layer (30, fig4B, [81]) comprising a plurality of pockets (space between 30, fig2 and 4B, [81]) overlapping the plurality of first assembly wirings (21, fig2 and 4B, [58]) and the plurality of second assembly wirings (22, fig2 and 4B, [58]); and a plurality of light emitting devices (40, fig2 and 3A, [65]) disposed in the plurality of pockets in each of the plurality of sub pixels and comprising a lower electrode (410 or 420, fig3A, [65]) connected to the display device, wherein each of the plurality of pockets (space between 30, fig2 and 4B, [81]) comprises a first pocket (pocket between 31 and 32, fig4B, [81]) having a first size and in which the plurality of light emitting devices are disposed, and a second pocket (pocket between 30 and 31 and pocket between 30 and 32, fig4B) having a second size smaller than the first size and extending from the first pocket. Re Claim 13 , Im teaches the display device according to claim 12, wherein the plurality of first assembly wirings (21, fig2 and 4B, [58]) are disposed above the plurality of second assembly wirings (22, fig2 and 4B, [58]), wherein the lower electrode (410 or 420 in contact with 21, fig3A and 4B) is in contact with the plurality of first assembly wirings, and wherein the second pocket (pocket between 30 and 31 and pocket between 30 and 32, fig4B) overlaps the plurality of first assembly wiring (pocket between 30 and 31 overlap with part of 21 between 30 and 31, fig4B), Re Claim 14 , Im teaches the display device according to claim 12, wherein the plurality of first assembly wirings (21, fig2 and 4B, [58]) and the plurality of second assembly wirings (22, fig2 and 4B, [58]) are arranged on a same plane (105, fig4B, [161]), Re Claim 18 , Im teaches the display device according to claim 14, wherein the second pockets (pocket between 30 and 31 and pocket between 30 and 32, fig4B) are arranged in plurality to surround the outside of the first pocket (pocket between 31 and 32, fig4B, [81]). Re Claim20 , Im teaches a display device (fig1) having a semiconductor light emitting device (40, fig2 and 3A, [65]), comprising: a substrate (100, fig4B, [79]); a first assembly wiring (21, fig2 and 4B, [58]) and a second assembly wiring (22, fig2 and 4B, [58]) arranged to be spaced apart from each other on the substrate; a planarization layer (30, 31, 32, fig4B, [81, 82]) disposed on the first assembly wiring and the second assembly wiring and having an opening (space around 30, 31, 32, fig2 and 4B, [81, 82]) overlapping the first assembly wiring and the second assembly wiring; a light emitting device (40, fig2 and 3A, [65]) disposed within the opening and comprising a first electrode (410 or 420, fig3A, [65]); a side wiring (61 or 62, fig4B, [63]) disposed within the opening and electrically connected to the first electrode (410 or 420, fig3A, [65]); and wherein the opening comprises a main opening (opening between 31 and 32, fig4B, [81]) and one or more auxiliary openings (opening between 30 and 31 and opening between 30 and 32, fig4B) connected to the main opening and smaller than the main opening, and wherein the side wiring (61 or 62, fig4B, [63]) is disposed within the auxiliary opening (opening between 30 and 31 and opening between 30 and 32, fig4B) and is in contact with a side wall of the opening (side wall of 31 and side wall of 32, fig2 and 4B) . 07-15 AIA Claim (s) 1-3 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee et al. US 2020/0403030 . Re Claim1 , Lee teaches a display device (fig1) having a semiconductor light emitting device (300, fig4 and 5, [157, 160]), comprising: a substrate (110, fig4, [116]); a first assembly wiring (220, fig4, [116]) and a second assembly wiring (210, fig4, [116]) arranged to be spaced apart from each other on the substrate; a planarization layer (430, fig2 and 4, [131]) disposed on the first assembly wiring (220, fig2, [116]) and the second assembly wiring (210, fig2, [116]) and having an opening (region between 430 in fig4) overlapping the first assembly wiring and the second assembly wiring (fig3 and 4); and a light emitting device (300, fig4 and 5, [157]) disposed inside the opening and comprising a first electrode (370 or 310, fig5, [159, 165]) electrically connected to the first assembly wiring (one end with 370 or 310 connected to 220 via 262, fig4, [93]), wherein the opening comprises a main opening (center region between 420, fig4, [95]) and one or more auxiliary openings (opening between 430 and 420, fig4, [95]) connected to the main opening and smaller than the main opening (auxiliary region between 430 and 420 smaller than main opening between 420, fig2 and 4). Re Claim 2 , Lee teaches the display device according to claim 1, wherein the first assembly wiring (220, fig4, [116]) is disposed above the second assembly wiring (210, fig4, [116]), wherein the first electrode (370 or 310 in contact with 210, fig4 and 5, [159, 165]) is in contact with the first assembly wiring, and wherein the auxiliary opening (opening between 430 and 420, fig4, [95]) is configured to overlap the first assembly wiring (220, fig4, [116]). Re Claim 3 , Lee teaches the display device according to claim 2, wherein an area where the first assembly wiring (220, fig2 and 4, [116]) and the opening overlap is wider than an area where the second assembly wiring (210, fig2 and 4, [116]) and the opening overlap . 07-15 AIA Claim (s) 20 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chai et al WO 2020/071614 (US 2021/0399040 as English translation) . Re Claim20 , Chai teaches a display device (fig1 and2) having a semiconductor light emitting device (350, fig2 and 3, [134]), comprising: a substrate (110, fig2, [69]); a first assembly wiring (330, fig2, [95]) and a second assembly wiring (340, fig2, [95]) arranged to be spaced apart from each other on the substrate; a planarization layer (421, 422, fig2, [111]) disposed on the first assembly wiring and the second assembly wiring and having an opening (space between 421 and 422, fig2) overlapping the first assembly wiring and the second assembly wiring (fig2); a light emitting device (350, fig2 and 3, [65]) disposed within the opening and comprising a first electrode (351 or 352, fig3, [134]); a side wiring (360, fig2, [115]) disposed within the opening and electrically connected to the first electrode (351 or 352, fig3, [134]); and wherein the opening comprises a main opening (opening between 330 and 340, fig2) and one or more auxiliary openings (opening between 421 and 422 overlapping with 512 and 513, fig2) connected to the main opening and smaller than the main opening, and wherein the side wiring (360, fig2, [115]) is disposed within the auxiliary opening (opening between 421 and 422 overlapping with 512 and 513, fig2) and is in contact with a side wall of the opening (side wall of 421, fig2). Allowable Subject Matter Claim 4-11, 15-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. Specifically, the limitations are material to the inventive concept of the application in hand to reduce assembly defect by reducing electric field asymmetry phenomenon and improve assembly force by arranging multiple assembly lines to vertically overlap each other. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812 Application/Control Number: 18/713,565 Page 2 Art Unit: 2812 Application/Control Number: 18/713,565 Page 3 Art Unit: 2812 Application/Control Number: 18/713,565 Page 4 Art Unit: 2812 Application/Control Number: 18/713,565 Page 5 Art Unit: 2812 Application/Control Number: 18/713,565 Page 6 Art Unit: 2812 Application/Control Number: 18/713,565 Page 7 Art Unit: 2812 Application/Control Number: 18/713,565 Page 8 Art Unit: 2812 Application/Control Number: 18/713,565 Page 9 Art Unit: 2812
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