DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 05/28/2024. Claims 1-7 are pending in the Application, of which Claim 1 is independent.
Continuity/ Priority Information
The present Application 18714083 filed 05/28/2024 is a National Stage entry of PCT/CN2023/081508, International Filing Date: 03/15/2023 and claims foreign priority to CHINA, 202210536671.4, filed 05/18/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Drawings
Figure 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. FIG. 2 is a schematic diagram of a traditional pattern file. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) o as recited in Claim 1, r 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are, as recited in Claim 1, for example, the Claim fails to recite the essential structural cooperative relationships: a test processor (TP) (4), a Parameter Pattern compiler (PPC), a parameter test controller (PTC), and an instruments control bus (ICB), wherein the TP (4) comprises a timing generator (TG) (1), a pattern generator (2), a signal processor unit command generator (3), a pattern memory, a memory control, and an instruments control message generator (ICMG) (5).
Also, the claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim 1, “vector is composed of a pattern generator command (11)” “the analog device pin list (15) is composed of instrument control opcodes” is indefinite language.
Claim 2, “combination vector is referred to as an instrument control opcode group” is indefinite.
Any Claims not specifically mentioned above are rejected due to their dependency on an rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ru et al. (Pub. No. US 20220317185) Date filed: 2021-05-04.
Regarding independent Claim 1, Ru discloses a pattern generation system and a method for providing source signals to test channels in a test equipment, comprising:
A concurrent testing device for an integrated circuit, comprising a test processor (TP) (4), a Parameter Pattern compiler (PPC), a parameter test controller (PTC), and an instruments control bus (ICB), wherein the TP (4) comprises a timing generator (TG) (1), a pattern generator (2), a signal processor unit command generator (3), a pattern memory, a memory control, and an instruments control message generator (ICMG) (5);
[0033] FIG. 1 illustrates a test environment 100 including a test equipment 101 and a DUT 128. Test equipment 101 can be an automatic test equipment (ATE), or any other integrated circuit tester that is capable of performing a test for DUT 128. By way of examples, FIG. 1 shows that test equipment 101 is coupled to one DUT 128. In practice, test equipment 101 may be coupled to a plurality of DUTs 128 and perform tests for the plurality of DUTs 128 simultaneously, corresponding to “concurrent testing device for an integrated circuit”.
[0034] In some implementations, test equipment 101 may include a pattern generation system 102 and a set of test channels 126A, . . . , 126N (also referred to as test channel 126 collectively or individually). Each test channel 126 is coupled to a pin of DUT 128, and drives the pin to carry out a test activity on the pin. For example, test channel 126A is coupled to pin A of DUT 128, and test channel 126N is coupled to pin N of DUT 128. In some implementations, each test channel 126 may be coupled to multiple pins from multiple DUTs 128 simultaneously
[0035] In some implementations, pattern generation system 102 may include an input/output (I/O) interface 104, a timing generator 106, a processor 108, a memory 110, a pattern generator 114, a pin function configurator 122, and a set of source selectors 124A, . . . , 124N (also referred to as source selector 124 collectively or individually).
[0037] Timing generator 106 can be configured to generate clock signals and provide the clock signals to other components of pattern generation system 102 and the set of test channels 126. For example, timing generator 106 includes a clock generator for generating the clock signals.
[0038] Processor 108 can be configured to send or receive data to or from memory 110. For example, processor 108 can be configured to receive instructions from memory 110 and execute the instructions to provide the functionality described herein.
the digital channel list (13) is used for describing working states of various digital channels under different timing conditions in each cycle; the analog device pin list (15) is composed of instrument control opcodes; the PPC converts the instrument control opcodes into instruments control messages (ICM) according to a conversion table for instrument control opcodes and ICMs; and the PPC is connected to the PTC through the ICB.
[0067] With reference to FIGS. 3A-3B, At the test cycle n, pin function configurator 122 can determine the value of the pin function index to be p0 based on the first instruction, and search lookup table 304A and lookup table 304N using the value p0 of the pin function index. Pin function configurator 122 can obtain index mapping data 324A from lookup table 304A and index mapping data 324N from lookup table 304N based on the value p0 of the pin function index.
[0098] FIG. 5 illustrates a graphic representation 500 of exemplary lookup tables 304, according to some aspects of the present disclosure. Table 1 illustrates an example of lookup table 304A for test channel 126A. Table 2 illustrates an example of lookup table 304N for test channel 126N.
Regarding Claims 2-4, Ru discloses instrument control opcode [0046] Pin function configurator 122 can be configured to perform a pin function mapping for the set of test channels 126 (or equivalently, for a set of pins that is respectively coupled to the set of test channels 126). For example, pin function configurator 122 can retrieve instructions 112 from memory 110, and generate a set of source selection signals for the set of test channels 126 based on instructions 112. Pin function configurator 122 can provide the set of source selection signals to the set of source selectors 124 that is coupled to the set of test channels 126, respectively. Then, each source selector 124 multiplexes the plurality of source patterns to a test channel 126 based on a source selection signal provided to the respective source selector 124. As a result, a mapping from the plurality of source patterns to test channel 126 (as well as a pin function mapping for a pin coupled to test channel 126) can be achieved. Pin function configurator 122 is described below in more detail with reference to FIGS. 2A-6.
Regarding Claims 5-7, Ru discloses testing method of the concurrent testing device for the integrated circuit.
[0081] FIG. 4C illustrates a graphic representation 440 for providing source signals to test channels 126 with reference to the pin function mapping process in FIGS. 4A-4B, according to some aspects of the present disclosure. An instruction can include one or more of a pin-mapping operation PF_OP and operation data PF_OPD. Pin function mapper 410 may include an adder 442 configured to perform the pin-mapping operation.
[0082] At a test cycle, pin function mapper 410 can execute the pin-mapping operation PF_OP to generate an updated value for the pin function index based on one or more of: (1) lookup tables 304; (2) a latest value of the pin function index stored in pin function register 402; and (3) the operation data PF_OPD. Next, pin function mapper 410 can search lookup table 304A and lookup table 304N using the updated value of the pin function index, and obtain index mapping data 324A from lookup table 304A and index mapping data 324N from lookup table 304N. Pin function mapper 410 can generate source selection signal 204A for test channel 126A based on index mapping data 324A, and generate source selection signal 204N for test channel 126N based on index mapping data 324N. Source selector 124A may select a first source signal from the plurality of source patterns based on source selection signal 204A, and provide the first source signal to test channel 126A. Then, test channel 126A may drive pin A of DUT 128A and pin A of DUT 128N based on the first source signal.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 16, 2026
Non-Final Rejection 20260615
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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