DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/30/2024 and 05/29/2024 have been considered by the Examiner.
Claim Objections
Claim(s) 3, 5 and 12 are objected to because of the following informalities:
Claim 3 should replace “:” with a period “.” at the end.
Claim 5 recites a term “a first terminal of the second transistor” in line 4. Examiner suggests amending the term to recite “the first terminal of the second transistor” to restore clarity.
Claim 12 recites a phrase “configured to coupled …” in line 3. Examiner suggests amending the phrase to recite “configured to be coupled to …” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wang et al. (US 7626527; hereinafter Wang).
Regarding claim 1, Wang discloses in figure(s) 1-5 a detection circuit, comprising:
a threshold voltage generation circuit for generating a threshold voltage (col. 3 lines 10-20 :- threshold value is determined based on a modulation index of the CT .SIGMA..DELTA.ADC, which is the maximum input stability range of the CT .SIGMA..DELTA.ADC when referring to the reference voltage);
a voltage-to-current conversion circuit (308; figs. 3-4) for converting an offset voltage of a signal to be detected with respect to the threshold voltage into a proportional current (col. 5 line 20 - high linearity transconductance implies proportional current); and
a current-type successive approximation quantizer (304) which is used to obtain a detection result (col. 3 lines 50-55 :- adjusting variable transconductance DACp DACN to relax a dynamic range of the CT .SIGMA..DELTA.ADC; fig. 5) by quantizing the proportional current (col. 3 lines 50-55 :- when there is a non-linear disturbance at an input of the operational amplifier, and adjusting a transconductance of the voltage-to-current converter to relax a dynamic range of the CT .SIGMA..DELTA.ADC).
Regarding claim 2, Wang discloses in figure(s) 1-5 the detection circuit according to claim 1, wherein the detection result is a comparison result of the signal to be detected and the threshold voltage, or a quantization result of the signal to be detected within a window defined by the threshold voltage (col. 1 lines 60-65 :- quantizer 104 divides a continuous range of values of a wave into a finite number of sub-ranges. Each sub-range of the wave may be represented by an assigned or quantized value; fig. 1).
Regarding claim 3, Wang discloses in figure(s) 1-5 the detection circuit according to claim 2, further comprising: a differential sampling switch configured to provide the voltage-to-current conversion circuit with an offset voltage or a reference ground (col. 3 lines 1-10 :- a reset switch coupled to the at least one capacitor, the operational amplifier, and the feedback mechanism, and a single directional voltage-to-current converter coupled to the input terminal; fig. 3).
Regarding claim 16, Wang discloses in figure(s) 1-5 a power management system (col. 5 lines 59-61 :- regulate the transconductance to provide an effective 20 dB gain to the system. This provides power and area savings), comprising the detection circuit according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of UEHARA et al. (US 20160269011).
Regarding claim 13, Wang teaches in figure(s) 1-14 the detection circuit according to claim 1,
Wang does not teach explicitly wherein the detection circuit has a plurality of input terminals, and the detection circuit is configured to detect signals to be detected at the plurality of input terminals in a time-division manner.
However, UEHARA teaches in figure(s) <fs2num_1> wherein the detection circuit has a plurality of input terminals, and the detection circuit is configured to detect signals to be detected at the plurality of input terminals in a time-division manner (para. 8 - a multiplexer that selects an input signal from first to n-th input signals (n is an integer greater than or equal to 2) inputted to first to n-th nodes in a time division manner and outputs the selected input signal to an output node; fig. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wang by having wherein the detection circuit has a plurality of input terminals, and the detection circuit is configured to detect signals to be detected at the plurality of input terminals in a time-division manner as taught by UEHARA in order to provide scale and accuracy as evidenced by "an accurate A/D-converted value even when a circuit in a stage upstream of a multiplexer has poor driving capability" (para. 7 of UEHARA).
Claim(s) 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of UEHARA, and further in view of Bogner et al. (US 8564470).
Regarding claim 14, Wang in view of UEHARA teaches the detection circuit according to claim 13,
Wang does not teach explicitly further comprising a register array for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generation circuit generating threshold voltages respectively according to the control codes provided by the register array.
However, Bogner teaches in figure(s) 1-4 further comprising a register array (R, SAR; figs. 1,4; col. 3 lines 15-17 - a register R for storing the digital register value x.sub.COUNT as well as a control circuit CTRL that is responsive to the comparator circuit's output.) for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generation circuit generating threshold voltages respectively according to the control codes provided by the register array (abs. - Control circuitry is responsive to the comparator circuit and is configured to adjust the digital register value stored in the register and to adjust the reference current until the comparator indicates that the potential of the circuit node does not deviate from the desired value.).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wang by having further comprising a register array for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generation circuit generating threshold voltages respectively according to the control codes provided by the register array as taught by Bogner in order to provide efficient execution as evidenced by "an analog-to-digital conversion circuit includes a register for storing a digital register value and a digital-to-analog converter that is configured to provide a reference current at a circuit node which is set in accordance to the digital register value" (abstract).
Regarding claim 15, Wang as modified by UEHARA and Bogner teaches the detection circuit according to claim 14,
wherein the threshold voltage generation circuit is a capacitive digital-to-analog converter (capacitive DAC 306 in fig. 4 of Wang or capacitive DAC in fig. 4 of Bogner).
Allowable Subject Matter
Claim(s) 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior arts of record do not fairly teach or suggest “wherein the voltage-to-current conversion circuit comprises: a storage capacitor, with a first end being coupled with an output of the threshold generation circuit and an input terminal for receiving the signal to be detected; a first transistor having a control terminal being coupled with a second end of the storage capacitor; a first resistor having a first end being coupled with a second terminal of the first transistor, and a second end being coupled to the offset voltage or the reference ground via the differential sampling switch; and a second transistor having a control terminal for receiving a bias voltage, a second terminal being coupled with a first terminal of the first transistor, and a first terminal for outputting the proportional current” including all of the limitations of the base claim and any intervening claims.
Claim(s) 5-12 are objected for dependent upon base claim 4.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See the List of References cited in the US PT0-892.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858