DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The preliminary Amendment filed 29 May 2024 has been entered and considered. Claims 5 and 7-13 have been amended. Claims 1-16 are all the claims pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/29/2024 and 10/23/2025 were considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 and 14-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ishikawa et al. (U.S. Patent App. Pub No. 2003/0158608 A1, hereafter referred as Ishikawa).
Regarding Claim 1:
Ishikawa teaches a picture image processing apparatus comprising (Ishikawa: Par. [0001]; data processing apparatus): a circuit device (Ishikawa: Par. [0332]; MCU reducing circuit 352 reduces an MCU size in the valid range to a predetermined size) having a horizontal reduction circuit that reduces input picture image data in a horizontal direction at a specified horizontal reduction rate (Ishikawa: Par. [0332-0333]; the MCU reducing circuit 352 is comprised of two reducing circuits, i.e., a horizontal size reducing circuit 361 and vertical size reducing circuit 362; the valid signal generating circuit 363 increments the internal horizontal and vertical counters in accordance with the input valid signal), and a vertical reduction circuit that reduces input picture image data in a vertical direction at a specified vertical reduction rate (Ishikawa: Par. [0332-0333]; the MCU reducing circuit 352 is comprised of two reducing circuits, i.e., a horizontal size reducing circuit 361 and vertical size reducing circuit 362; the valid signal generating circuit 363 increments the internal horizontal and vertical counters in accordance with the input valid signal).
In regards to Claim 2, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein the circuit device reduces the picture image data in the horizontal direction by the horizontal reduction circuit, and reduces the picture image data, which has been reduced in the horizontal direction, in the vertical direction by the vertical reduction circuit (Ishikawa: Par. [0291] and Fig. 35; the same reducing circuit can be used in both the horizontal direction and the vertical direction; Fig. 35 shows output of horizontal size reducing circuit is input for vertical size reducing circuit).
In regards to Claim 3, Ishikawa further teaches the picture image processing apparatus according to claim 2, wherein the picture image data is input to the horizontal reduction circuit in a unit of a picture cell group including a plurality of picture cells arrayed in the horizontal direction (Ishikawa: Par. [0273]; the input unit 185 extracts neighboring frame pixel data necessary for frame resizing processing), and the horizontal reduction circuit includes a horizontal picture cell shift amount calculator that calculates, based on the horizontal reduction rate, a shift amount of each of the plurality of picture cells in the horizontal direction for reducing the picture image data in the horizontal direction (Ishikawa: Par. [0273]; the MAC unit 186 performs multiplying and accumulating for the neighboring frame pixel data and an interpolation coefficient; the MAC unit 186 operates as an interpolation filter), a horizontal shift picture cell value calculator that calculates a horizontal shift picture cell value, which is a picture cell value of each of the plurality of picture cells after shift in the horizontal direction, based on a picture cell value of each of the plurality of picture cells and the horizontal shift amount (Ishikawa: Par. [0273]; the alpha value accompanying the frame pixel data is also interpolated; the input unit 185 also input pixel data to the alpha blending unit 187), a horizontal picture cell shifter that shifts each of the plurality of picture cells, for which the horizontal shift picture cell values have been calculated and which has been arrayed in the vertical direction, in the horizontal direction based on the horizontal shift amount of the picture cell (Ishikawa: Par. [0273]; the alpha blending unit 187 blends the output from the MAC unit 186 with the above pixel data by using the alpha value of the MAC output), a horizontal shift picture cell value adder that adds up the horizontal shift picture cell values of the plurality of picture cells shifted in the horizontal direction for each picture cell position in the horizontal direction (Ishikawa: Par. [0273]; the alpha blending unit 187 blends the output from the MAC unit 186 with the above pixel data by using the alpha value of the MAC output), and a horizontally-reduced picture image data former that forms, using a horizontal shift picture cell value addition result, horizontally-reduced picture image data obtained by reducing the picture image data in the horizontal direction (Ishikawa: Par. [0273]; the output unit 188 then outputs the resultant data to the shared memory; the clipping processing is implemented by memory access by the input unit 185 which makes it possible to composite data while resizing frame data).
In regards to Claim 4, Ishikawa further teaches the picture image processing apparatus according to claim 3, wherein the horizontal shift picture cell value calculator divides the picture cell value of each of the plurality of picture cells based on the horizontal reduction rate, and as the horizontal shift picture cell value, outputs an added value obtained by addition of a picture cell value corresponding to a picture cell after shift in the horizontal direction among the divided values (Ishikawa: Par. [0273]; the MAC unit 186 performs multiplying and accumulating for the neighboring frame pixel data and an interpolation coefficient; the MAC unit 186 operates as an interpolation filter; the alpha value accompanying the frame pixel data is also interpolated).
In regards to Claim 5, Ishikawa further teaches the picture image processing apparatus according to claim 3, wherein the horizontally-reduced picture image data is input to the vertical reduction circuit in a unit of a picture cell group including a plurality of picture cells arrayed in the horizontal direction (Ishikawa: Par. [0273]; the input unit 185 extracts neighboring frame pixel data necessary for frame resizing processing), and the vertical reduction circuit includes a vertical picture cell shift amount calculator that calculates, based on the vertical reduction rate, a shift amount of each of the plurality of picture cells in the vertical direction for reducing the picture image data in the vertical direction (Ishikawa: Par. [0273]; the MAC unit 186 performs multiplying and accumulating for the neighboring frame pixel data and an interpolation coefficient; the MAC unit 186 operates as an interpolation filter), a vertical shift picture cell value calculator that calculates a vertical shift picture cell value, which is a picture cell value of each of the plurality of picture cells after shift in the vertical direction, based on a picture cell value of each of the plurality of picture cells and the vertical shift amount (Ishikawa: Par. [0273]; the alpha value accompanying the frame pixel data is also interpolated; the input unit 185 also input pixel data to the alpha blending unit 187), a vertical picture cell shifter that shifts each of the plurality of picture cells, for which the vertical shift picture cell values have been calculated and which has been arrayed in the horizontal direction, in the vertical direction based on the vertical shift amount of the picture cell (Ishikawa: Par. [0273]; the alpha value accompanying the frame pixel data is also interpolated; the input unit 185 also input pixel data to the alpha blending unit 187), and a vertical shift picture cell value adder that adds up the vertical shift picture cell values of the plurality of picture cells shifted in the vertical direction for each picture cell position in the vertical direction (Ishikawa: Par. [0273]; the alpha blending unit 187 blends the output from the MAC unit 186 with the above pixel data by using the alpha value of the MAC output).
In regards to Claim 6, Ishikawa further teaches the picture image processing apparatus according to claim 5, wherein an identical vertical shift amount is applied to the plurality of picture cells (Ishikawa: Par. [0333] and Fig. 35; a value y from the vertical counter is supplied to the vertical size reducing circuit 362; each value is used to select an interpolation coefficient; the figure showcases that the vertical size reduction circuit gets its input signal from the valid signal generating circuit (y) meaning it can be set as identical values).
In regards to Claim 7, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein the horizontal reduction circuit includes a multiplier, an adder (Ishikawa: Par. [0267]; a multiplier and accumulator (MAC) unit), and a register (Ishikawa: Par. [0291]; a register corresponding to the number of pixels of a block in the horizontal direction is required between a reducing circuit in the horizontal direction and a reducing circuit in the vertical direction).
In regards to Claim 8, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein the vertical reduction circuit includes a multiplier, an adder (Ishikawa: Par. [0267]; a multiplier and accumulator (MAC) unit), and a line buffer (Ishikawa: Par. [0480]; if a line memory is provided for the resizing circuit 359, such operation can be realized by only reading out image data from the start).
In regards to Claim 9, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein the horizontal reduction circuit is able to reduce the picture image data in the horizontal direction at the horizontal reduction rate whose inverse is not an integer (Ishikawa: Par. [0479]; he MCU reducing circuit 352 therefore reduces the image to 3/8).
In regards to Claim 10, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein the vertical reduction circuit is able to reduce the picture image data in the vertical direction at the vertical reduction rate whose inverse is not an integer (Ishikawa: Par. [0479]; he MCU reducing circuit 352 therefore reduces the image to 3/8).
In regards to Claim 11, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein different values are able to be specified as the horizontal reduction rate and the vertical reduction rate (Ishikawa: Fig. 35; the figure showcases that the horizontal and vertical size reduction circuits are separate with separate input signals from the valid signal generating circuit (x, y) meaning they can be independently set as different values).
In regards to Claim 12, Ishikawa further teaches the picture image processing apparatus according to claim 1, wherein an identical value is able to be specified as the horizontal reduction rate and the vertical reduction rate (Ishikawa: Fig. 35; the figure showcases that the horizontal and vertical size reduction circuits are separate with separate input signals from the valid signal generating circuit (x, y) meaning they can be independently set as identical values).
In regards to Claim 14, Ishikawa further teaches an imaging apparatus comprising: an imaging element that images an object and outputs picture image data on a picture image of the object; and the picture image processing apparatus according to claim 1, that processes the picture image data output from the imaging element (Ishikawa: Par. [0008]; arrangement of a conventional image processor which performs image processing when image data taken by a digital camera).
In regards to Claim 15, Ishikawa further teaches the imaging apparatus according to claim 14, further comprising: an input with which a user inputs the horizontal reduction rate and the vertical reduction rate (Ishikawa: Par. [0333]; a value x from the horizontal counter is supplied to the horizontal size reducing circuit 361; a value y from the vertical counter is supplied to the vertical size reducing circuit 362; each value is used to select an interpolation coefficient; the values x and y from the horizontal and vertical counters are input to a valid signal table and converted into valid signals; the valid signal table has an 8-bit output for each reduction size, and selects one bit in accordance with the value of each counter).
Regarding Claim 16:
Ishikawa further teaches a picture image processing method comprising (Ishikawa: Par. [0001]; data processing by exchanging data through a memory, an image processing apparatus, and a method for these apparatuses): a step of reducing input picture image data in a horizontal direction at a specified horizontal reduction rate (Ishikawa: Par. [0332-0333]; the MCU reducing circuit 352 is comprised of two reducing circuits, i.e., a horizontal size reducing circuit 361 and vertical size reducing circuit 362; the valid signal generating circuit 363 increments the internal horizontal and vertical counters in accordance with the input valid signal); and a step of reducing the picture image data, which has been reduced in the horizontal direction (Ishikawa: Par. [0291] and Fig. 35; the same reducing circuit can be used in both the horizontal direction and the vertical direction; Fig. 35 shows output of horizontal size reducing circuit is input for vertical size reducing circuit), in a vertical direction at a specified vertical reduction rate (Ishikawa: Par. [0332-0333]; the MCU reducing circuit 352 is comprised of two reducing circuits, i.e., a horizontal size reducing circuit 361 and vertical size reducing circuit 362; the valid signal generating circuit 363 increments the internal horizontal and vertical counters in accordance with the input valid signal).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa et al. (U.S. Patent App. Pub No. 2003/0158608 A1, hereafter referred as Ishikawa) in view of Kobayashi et al. (J.P. Patent Pub No. 2006024998 A, hereafter referred as Kobayashi).
In regards to Claim 13, Ishikawa fails to further teach the picture image processing apparatus according to claim 1, wherein the circuit device further includes a horizontal separation circuit that color-separates Bayer array picture image data in the horizontal direction, and a horizontal interweaving circuit that interweaves the picture image data, which has been processed via the horizontal separation circuit, in the horizontal direction, and the circuit device color-separates the Bayer array picture image data in the horizontal direction by the horizontal separation circuit, reduces the color-separated picture image data in the horizontal direction by the horizontal reduction circuit, and interweaves the picture image data, which has been color-separated and reduced in the horizontal direction, in the horizontal direction by the horizontal interweaving circuit.
Kobayashi, like Ishikawa, is directed to picture image processing apparatus, an imaging apparatus, and a picture image processing method. Kobayashi does teach wherein the circuit device further includes a horizontal separation circuit that color-separates Bayer array picture image data in the horizontal direction (Kobayashi: Par. [0027]; the image signal outputted from the image pickup sensor 1 is an image signal of an RGB Bayer array, reduction interpolation processing of the present invention can be applied to various image signals such as an image signal outputted from an image pickup sensor including a color filter array of a complementary color system), and a horizontal interweaving circuit that interweaves the picture image data, which has been processed via the horizontal separation circuit, in the horizontal direction, and the circuit device color-separates the Bayer array picture image data in the horizontal direction by the horizontal separation circuit, reduces the color-separated picture image data in the horizontal direction by the horizontal reduction circuit, and interweaves the picture image data, which has been color-separated and reduced in the horizontal direction, in the horizontal direction by the horizontal interweaving circuit (Kobayashi: Par. [0015]; the input image signal includes an image signal of an RGB Bayer array, and a two dimensional image is reduced to LV / RV by applying the processing in each circuit according to the fifth or sixth aspect to a horizontal direction and a vertical direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ishikawa to utilize the Bayer array method, as taught by Kobayashi, to arrive at the claimed invention discussed above. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. As taught by Kobayashi, the proposed modification is capable of performing high-precision reduction interpolation processing for each color component of a color image signal (Kobayashi: Par. [0008]).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Murakami (U.S. Patent App. Pub No. 2012/0293650 A1) teaches a data reduction processing unit that reduces data volume of image data of the object if the stain method estimated by the stain method estimation unit is a predetermined stain method.
Tatsuzawa et al. (U.S. Patent App. Pub No. 2014/0153841 A1) teaches an image processing device includes a line memory that stores an input image by a plurality of rows.
Conclusion
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/RENAE A BITOR/Examiner, Art Unit 2663
/GREGORY A MORSE/Supervisory Patent Examiner, Art Unit 2698
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