Prosecution Insights
Last updated: October 02, 2026
Application No. 18/714,232

WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

Non-Final OA §102
Filed
May 29, 2024
Priority
Nov 30, 2021 — JP 2021-193727 +1 more
Examiner
ESTRADA, ANGEL R
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kyocera Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
42%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1168 granted / 1366 resolved
+17.5% vs TC avg
Minimal -43% lift
Without
With
+-43.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
1385
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
38.2%
-1.8% vs TC avg
§102
53.4%
+13.4% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1366 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on May 29, 2024 and June 3, 2025 have been considered by the Examiner. Claim Objections Claims 6, 19 and 20 are objected to because of the following informalities: In claim 6, 19 and 20 line 4, change “the second line ” to --the third line--. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 7, 10-13, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoyama (US 8,822,831) Regarding claim 1, Yokoyama discloses a wiring substrate (7; see figure 5c) comprising: an insulating substrate (8); a first line (9a, 16a, 10a,14a,11a) and a second line (9b,16a, 10b, 14b,11b) positioned adjacent to each other on the insulating substrate (8, see figure 5b); and a ground film conductor (19) and a ground via conductor positioned on the insulating substrate (8) and surrounding the first line (9a,16a, 10a,14a,11a) and the second line (9b,16b,10b,14b,11b); wherein the first line (9a,10a,16a14a,11a) includes a first line conductor (9a; see figure 5c), a first via conductor (12a) connected to the first line conductor (9a, see figure 5c), a second line conductor (10a; see figure 5c) connected to the first via conductor (12a; see figure 5c) and extending opposite from the first line conductor (9a) with the first via conductor (12a) being interposed therebetween in a plan perspective view (see figure 5a and 5c), and a second via conductor (13a) connected to the second line conductor (10a) and extending to a layer different from a layer including the first via conductor (12a; see figure 5c), the second line (9b, 16b, 10b, 14b,11b) includes a third line conductor (9b), a third via conductor (12b) connected to the third line conductor (9b), a fourth line conductor (10b) connected to the third via conductor (12b) and extending opposite from the third line conductor (9b) with the third via conductor (12b) being interposed therebetween in a plan perspective view, and a fourth via conductor (13b) connected to the fourth line conductor (10b) and extending to a layer different from a layer including the third via conductor (12b), in a plan perspective view (see figures 5a and 5c), the first line conductor (9a) and the third line conductor (9b) include portions having a distance increasing toward the first via conductor (12a) and the third via conductor (12b), and the second line conductor (10a) and the fourth line conductor (10b) include portions having a distance decreasing toward the second via conductor (13b) and the fourth via conductor (13b). Regarding claim 2, Yokoyama discloses the wiring substrate (7; see figure 5c), wherein the first line conductor (9a) and the second line conductor (10a) are spaced apart from each other in a thickness direction of the insulating substrate (8), and the third line conductor (9b) and the fourth line conductor (10b) are spaced apart from each other in the thickness direction of the insulating substrate (see figure 5c). Regarding claim 3, Yokoyama discloses the wiring substrate (7; see figure 5c), wherein the insulating substrate (8) includes a first surface and a second surface positioned opposite to the first surface (see figure 5c), the first line conductor (9a) and the third line conductor (9b) are positioned closer to the first surface than the second surface (see figure 5c), and the second line conductor (10a) and the fourth line conductor (10b) are positioned closer to the second surface than the first surface (see figure 5c). Regarding claim 4, Yokoyama disclose the wiring substrate (7; see figure 5c), wherein the ground film conductor (19) includes a first ground film conductor including a first opening (18a; 18b, see figure 5a), and a second ground film conductor including a second opening (21a, 21b), the first via conductor (12a) and the third via conductor (12b) are at least partially positioned in the first opening (18a,18b; see figure 5a), the second via conductor (13a) and the fourth via conductor (13b) are at least partially positioned in the second opening (21a, 21b), and the first opening is smaller than the second opening (see figure 5a and 5c). Regarding claim 6 , Yokoyama discloses the wiring substrate (7; see figure 5c), wherein the first line conductor (9a) further includes a first parallel line conductor connected to the first line conductor (9a) on an opposite side of the first via conductor (12a), the third line conductor (9b) further includes a second parallel line conductor connected to the third line conductor (9b) on an opposite side of the third via conductor (12b), the first parallel line conductor and the second parallel line conductor are parallel with each other, and in a plan perspective view, the first opening includes a center part positioned between the first and second parallel line conductors and a center part of the second opening (see figure 5a). Regarding claim 7, Yokoyama discloses the wiring substrate (7; see figure 5c), wherein in a plan perspective view, the first opening (18a,18b; see figure 5a) includes a center part matching a center part of the second opening (see figure 5a). Regarding claim 10, Yokoyama discloses an electronic device comprising: the wiring substrate (7) and an electron element mounted on the wiring substrate (column 1 lines 6-13; electronic apparatuses). Regarding claim 11, Yokoyama discloses an electronic device comprising: the electronic device; and a module substrate equipped with the electronic device (column 1 lines 6-13; electronic apparatuses). Regarding claim 12, Yokoyama disclose the wiring substrate (7; see figure 5c), wherein the ground film conductor (19) includes a first ground film conductor including a first opening (18a; 18b, see figure 5a), and a second ground film conductor including a second opening (21a, 21b), the first via conductor (12a) and the third via conductor (12b) are at least partially positioned in the first opening (18a,18b; see figure 5a), the second via conductor (13a) and the fourth via conductor (13b) are at least partially positioned in the second opening (21a, 21b), and the first opening is smaller than the second opening (see figure 5a and 5c). Regarding claim 13, Yokoyama disclose the wiring substrate (7; see figure 5c), wherein the ground film conductor (19) includes a first ground film conductor including a first opening (18a; 18b, see figure 5a), and a second ground film conductor including a second opening (21a, 21b), the first via conductor (12a) and the third via conductor (12b) are at least partially positioned in the first opening (18a,18b; see figure 5a), the second via conductor (13a) and the fourth via conductor (13b) are at least partially positioned in the second opening (21a, 21b), and the first opening is smaller than the second opening (see figure 5a and 5c). Regarding claim 19 , Yokoyama discloses the wiring substrate (7; see figure 5c), wherein the first line conductor (9a) further includes a first parallel line conductor connected to the first line conductor (9a) on an opposite side of the first via conductor (12a), the third line conductor (9b) further includes a second parallel line conductor connected to the third line conductor (9b) on an opposite side of the third via conductor (12b), the first parallel line conductor and the second parallel line conductor are parallel with each other, and in a plan perspective view, the first opening includes a center part positioned between the first and second parallel line conductors and a center part of the second opening (see figure 5a). Regarding claim 20 , Yokoyama discloses the wiring substrate (7; see figure 5c), wherein the first line conductor (9a) further includes a first parallel line conductor connected to the first line conductor (9a) on an opposite side of the first via conductor (12a), the third line conductor (9b) further includes a second parallel line conductor connected to the third line conductor (9b) on an opposite side of the third via conductor (12b), the first parallel line conductor and the second parallel line conductor are parallel with each other, and in a plan perspective view, the first opening includes a center part positioned between the first and second parallel line conductors and a center part of the second opening (see figure 5a). Allowable Subject Matter Claims 5, 8, 9 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for allowance: The primary reasons for the indication of the allowability of claims 5, 8, 9 and 14-18 are: Regarding claim 5 , the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. Regarding claims 8 and 9 , the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate, wherein the insulating substrate includes a first surface and a second surface positioned opposite to the first surface, the first line further includes a first electrode positioned on the second surface, and an n-th via conductor connected to the first electrode ,the second line further includes a second electrode positioned on the second surface, and an (n+1)-th via conductor connected to the second electrode, the ground film conductor includes a third ground film conductor including a third opening ,in a perspective view in an aligning direction of the first electrode and the second electrode, the first via conductor and the third via conductor are positioned at a center of the first opening, and the n-th via conductor and the (n+1)-th via conductor are positioned at a center of the third opening. Regarding claim 14, the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate, wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. Regarding claim 15, the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate , wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. Regarding claim 16, the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate, wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. Regarding claim 17, the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate according to claim 3, wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. Regarding claim 18, the prior art does not teach or fairly suggest in combination with the other claimed limitations the wiring substrate, wherein the first line further includes a fifth line conductor connected to the second via conductor and extending opposite from the second line conductor with the second via conductor being interposed therebetween in a plan perspective view, a fifth via conductor connected to the fifth line conductor and extending to a layer different from a layer including the second via conductor, a sixth line conductor connected to the fifth via conductor and extending opposite from the fifth line conductor with the fifth via conductor being interposed therebetween in a plan perspective view, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from a layer including the fifth via conductor, the second line further includes a seventh line conductor connected to the fourth via conductor and extending opposite from the third line conductor with the fourth via conductor being interposed therebetween in a plan perspective view, a seventh via conductor connected to the seventh line conductor and extending to a layer different from a layer including the fourth via conductor, an eighth line conductor connected to the seventh via conductor and extending opposite from the seventh line conductor with the seventh via conductor being interposed therebetween in a plan perspective view, and an eighth via conductor connected to the eighth line conductor and extending to a layer different from a layer including the seventh via conductor, in a plan perspective view, the fifth line conductor and the seventh line conductor include portions having a distance increasing toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor include portions having a distance decreasing toward the sixth via conductor and the eighth via conductor. These limitations are found in claims 5, 8, 9 and 14-18, and are neither disclosed nor taught by the prior art of record, alone or in combination. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Morita et al (US 9,326,377), Regnier et al (US 7,448,909), Shimoda (US 7,193,490), Nagata et al (US 7,035,081) and Matsushita (US 10,827,613) disclose a wiring substrate. 7. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000. June 16, 2026 /ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
Read full office action

Prosecution Timeline

May 29, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102
Sep 22, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
42%
With Interview (-43.3%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1366 resolved cases by this examiner. Grant probability derived from career allowance rate.

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