DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 110707072 B (CN ‘072).
CN ‘072 discloses a system-in-package (SIP) assembly, wherein an integrated outer surface of a plastic package of the SIP assembly comprises
at least two shielding layer regions; and
a spacing region is provided between any two of the at least two shielding layer regions (see annotated figure below).
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Regarding claim 2, CN ‘072 discloses the SIP assembly according to claim 1, comprising a substrate (10) with at least two devices (20) provided on the substrate, wherein a position of the spacing region corresponds to a first region on the substrate; and
the first region comprises a region between mounting positions of any two of the at least two devices on the substrate (see image above).
Regarding claim 4, CN ‘072 discloses a method for packaging a system-in-package (SIP) assembly, comprising:
forming at least two shielding layer regions on an integrated outer surface of a plastic package of the SIP assembly, wherein a spacing region is provided between any two of the at least two shielding layer regions (see image above).
Regarding claim 5, CN ‘072 discloses the method for packaging an SIP assembly according to claim 4, wherein the SIP assembly comprises a substrate (10) with at least two devices (20) provided on the substrate; and
prior to said forming the at least two shielding layer regions on the integrated outer surface of the plastic package of the SIP assembly, the method comprises (opening groove/notch is located between two adjacent electronic components and that the groove route is taken between adjacent components; this corresponds to identifying a region on the substrate before forming the shielding structure. See Embodiment 1, S102, and Claim 3):
determining a first region on the substrate, the first region comprising a region between mounting positions of any two of the at least two devices on the substrate (notch/groove is located between two adjacent electronic components and that the groove may be arranged based on the position of the electronic components, including an L-shaped, U-shaped, square-shaped, or annular groove around a component. See Embodiment 1, FIG. 6 discussion, and Claim 3; and
determining a position of the spacing region based on the first region (opening groove/notch passes through the upper and lower surfaces of the plastic package body and is located between adjacent electronic components, and that the groove position corresponds to the component arrangement on the substrate. See Embodiment 1, S102, and Claim 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over CN ‘072.
Regarding claim 3, CN ‘072 SIP assembly according to claim 1, comprising a substrate (10) with at least one interfering source device (20) and at least one interfered device (20) corresponding to the interfering source device provided on the substrate,
wherein a position of the spacing region corresponds to a second region on the substrate (as shown in annotated figure); and
the second region comprises a region between a mounting position of the interfering source device on the substrate and a mounting position of the corresponding interfered device on the substrate (See, the Abstract; Embodiment 1; and Claims 1-3).
CN ‘072 further discloses that the notch may be arranged between adjacent electronic components to improve electromagnetic shielding between electronic components, and that the notch may also be formed as an annular groove with one electronic component located therein.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to position the spacing region of the claimed shielding layer based on the region between adjacent electronic components, or around a component in an annular configuration, because CN ‘072 expressly teaches that such groove placement and configuration improves electromagnetic isolation and shielding efficiency within the SIP module. Furthermore, to the extent claim 3 recites an interfering source device and a corresponding interfered device, CN ‘072’s adjacent electronic components perform the same EMI-related source/victim roles in the same packaging context, and selecting the spacing region between them would have been a predictable design choice for reducing interference and improving shielding performance. Accordingly, claim 3 would have been obvious over CN ‘072.
Regarding claim 6, CN ‘072 discloses the method for packaging an SIP assembly according to claim 4, wherein the SIP assembly comprises a substrate (10) with at least one interfering source device and at least one interfered device corresponding to the interfering source device provided on the substrate (CN 072 does not use the exact terms “interfering source device” and “interfered device” but it does disclose that the SIP module includes at least two electronic components on a substrate and that the package is designed to improve electromagnetic shielding between internal components. See Abstract, Background, Embodiment 1, and Claims 1, 3); and
prior to said forming the at least two shielding layer regions on the integrated outer surface of the plastic package of the SIP assembly, the method comprises (the groove/notch position based on the arrangement of the components on the substrate, i.e., the groove is formed between adjacent electronic components. See Embodiment 1, S102, and Claim 3):
determining a second region on the substrate, the second region comprising a region between a mounting position of the interfering source device on the substrate and a mounting position of the corresponding interfered device on the substrate (notch/groove is located between adjacent electronic components to separate components that interfere with each other and improve EMI shielding; this adjacent-component arrangement is the functional source/victim relationship relied upon for the obviousness mapping. See Background, Embodiment 1, and Claims 1 and 3); and
determining a position of the spacing region based on the second region (positioning the opening groove/notch between adjacent electronic components, and forming the conductive shielding layer on the upper surface and groove inner surface to improve electromagnetic isolation. See Abstract, Embodiment 1, S102-S103, and Claims 1 and 3).
It would have been obvious to a person of ordinary skill in the art before the effect filing date of the invention to treat the adjacent electronic components disclosed in CN ‘072 as corresponding respectively to an interfering source device and an interfered device, because CN ‘072 already identifies the disclosed components as having an EMI interference relationship and teaches positioning the notch between them to reduce such interference. The adjacent electronic components in CN ’072 perform the same functional source/victim roles recited in claim 6, and selecting the spacing region based on the region between their mounting positions would have been a predictable and routine design choice to achieve the known benefit of improved electromagnetic isolation. Accordingly, claim 6 would have been obvious over CN ‘072.
Regarding claim 7, CN ‘072 discloses a method for manufacturing a system-in-package (SIP) assembly, comprising (see Embodiment 1, S101-S104):
forming, based on an electromagnetic interference (EMI) coating process, a shielding layer on an integrated outer surface of a plastic package of the SIP assembly including the die (CN 072 discloses forming a conductive shielding layer on the upper surface of the plastic package body and on the inner surface of the groove by spraying or sputtering, See S103 and Claims 1 and 3.); and
wherein a position where the die is placed is a position of the spacing region (the groove/notch is located between two adjacent electronic components and that its position corresponds to the arrangement of components on the substrate, See S102, FIG. 6 discussion, and Claim 3).
CN ‘072 does not expressly disclose placing a die on the outer surface of the SIP assembly. CN ‘072 does not expressly disclose removing a die. It does disclose forming a groove/notch between adjacent electronic components, thereby creating a spacing region between shielding regions.
It would have been obvious to one of ordinary skill in the art before the effective filing date to use a temporary die, mask, or similar removable structure as a process equivalent to define the spacing region during shielding-layer formation, because CN ‘072 already teaches forming a separated shielding pattern on the package surface. The die-removal step is an obvious manufacturing variant of the disclosed groove-forming process. The claimed die functions as a temporary spacing/forming element that yields the same separated shielding regions achieved by CN ‘072.
Regarding claim 8, CN ‘072 discloses the method for manufacturing an SIP assembly according to claim 7, further comprising:
providing a substrate (10);
providing at least two devices (20) on a surface of the substrate;
performing plastic packaging (30) on the substrate to obtain the SIP assembly; and
manufacturing the die based on a position of a first region on the substrate (S102 and claim 3),
wherein the first region comprises a region between mounting positions of any two of the at least two devices on the substrate (Embodiment 1, S102, claim 3); or
manufacturing the die based on a position of a second region on the substrate, wherein the second region comprises a region between a mounting position of an interfering source device in the at least two devices on the substrate and a mounting position of a corresponding interfered device in the at least two devices on the substrate.
CN ‘072 does not expressly use the terms “interfering source device” or “interfered device.” CN ‘072 teaches the underlying EMI relationship between neighboring components.
It would have been obvious to one of ordinary skill in the art before the effective filing date to characterize one component as the interference source and the other as the affected component, and to locate the die based on that same separation region. Determining the die position based on the first region or second region would have been an obvious design choice yielding the predictable result of forming the shielding spacing region in the SIP package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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