DETAILED ACTION
Priority Claim
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
IDS
All references provided in the IDS dated 08/26/2024, 06/30/2025, 10/02/2025, 11/11/2025, 05/06/2026, and 06/24/2026 have been considered.
Drawings
The drawings are objected to because multiple figures contain multiple images labeled “a” “b” within a single figure. The subparts currently identified as “a” ...”b” should instead be presented as separate figures and labeled as (for example) “Fig. 3A”, “Fig. 3B”, respectively. It appears this occurs with Figs. 3-5, 8, 10, 12-17, 19-24, 26-29, 31-35. Examiner reminds applicant the changes should be implemented in the specification accordingly. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2 and 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Independent Claim 1,
Claim 1, line 16 recites: “the first inner surface side”. There is insufficient antecedent basis as no “a first inner surface side” has been claimed. It has been interpreted to mean any side of the first inner surface. Appropriate correction is required. Claims 2-10 are rejected by virtue of their dependency on Claim 1.
Claim 1, line 16 recites: “the first outer surface side”. There is insufficient antecedent basis as no “a first outer surface side” has been claimed. It has been interpreted to mean any side of the first outer surface. Appropriate correction is required. Claims 2-10 are rejected by virtue of their dependency on Claim 1.
Regarding dependent Claim 2,
Claim 2, lines 4-5 recites: “a contact portion provided to be exposed to an opposite side to the first chip side of the insulating layer”. There is insufficient antecedent basis as no “a first chip side of the insulating layer” has been claimed. It has been interpreted to mean that “a contact portion is provided on an opposite side of the insulating layer”. Appropriate correction is required.
Regarding dependent Claim 7,
Claim 7, lines 3-5 recites: “a second wiring electrically connected to the second terminal, passing through the inside of the first resin portion, and extending from the first inner surface side to the first outer surface side in the facing direction.” The corresponding structure, in view of the specification and drawings, cannot be understood. Even using broadest reasonable interpretation of first inner surface and first outer surface, is unclear how the second wiring (element 15, from Pg. 64 of the specification, Fig. 18) can possibly extend from the first inner surface to the first outer surface (elements 2a and 2b). Therefore, it has been interpreted to mean that “the second wiring electrically connected to the second terminal, passing through the inside of the first resin portion, in the facing direction”. Appropriate correction is required. Claims 8-10 are rejected by virtue of their dependency on Claim 7.
Claim 7, line 4 recites: “the first inner surface side”. There is insufficient antecedent basis for this as no “a first inner surface side” has been claimed. It has been interpreted to mean “any side”. Claims 8-10 are rejected by virtue of their dependency on Claim 7.
Claim 7, lines 4-5 recites: “the first outer surface side”. There is insufficient antecedent basis for this as no “a first outer surface side” has been claimed. It has been interpreted to mean “any side”. Claims 8-10 are rejected by virtue of their dependency on Claim 7.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-8 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kimura (US 20200066675 A1) in view of Shiraishi (US 20070015315 A1).
Re: Independent Claim 1, Kimura discloses:
An optical semiconductor package comprising:
a first chip being a semiconductor chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]) having a first inner surface (Kimura, Fig. 14, the top side of element 10D can be considered a first inner surface), a first outer surface being a surface on an opposite side of the first inner surface (Kimura, Fig. 14, the bottom side of element 10D can be considered a first outer surface), and a first side surface (Kimura, Fig. 14, the side of element 10D can be considered a first side surface) connecting the first inner surface and the first outer surface;
a second chip being a semiconductor chip (Kimura, semiconductor element; Fig. 14, element 10E, ¶ [0165]) disposed at a position facing the first inner surface (Kimura, Fig. 14 shows 10E disposed on the top side of 10D, therefore facing the first inner surface), the second chip having a second inner surface (Kimura, Fig. 14, the bottom side of element 10E can be considered a second inner surface) facing the first inner surface, a second outer surface being a surface on an opposite side of the second inner surface (Kimura, Fig. 14, the top side of element 10E can be considered a second outer surface and it is opposite the second inner surface), and a second side surface (Kimura, Fig. 14, the side of element 10E can be considered a second side surface) connecting the second inner surface and the second outer surface;
a first resin portion formed to cover at least the first side surface (Kimura, resin; Fig. 14, element 6, see attached annotated image label 1st resin portion, can be considered a first resin portion and covers the first side surface);
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a second resin portion formed to cover at least the second side surface (Kimura, resin; Fig. 14, element 6, see attached annotated image label 2nd resin portion, can be considered a second resin portion, and covers the second side surface);
a first terminal being an electrode terminal (Kimura, electrodes; Fig. 14, element 14, ¶ [0164], the left instance can be considered a first terminal) of the first chip and provided on the first inner surface (Kimura, Fig. 14 shows the electrode, element 14, on the top left side of element 10D, which is the first chip and the first inner surface);
a second terminal being an electrode terminal (Kimura, electrodes; Fig. 14, element 16, ¶ [0165]) of the second chip and provided on the second inner surface (Kimura, Fig. 14 shows the electrode, element 16, on the bottom side of the second chip, element 10E, and the second inner surface); and
the first resin portion and the second resin portion are integrally provided or continuously provided via another member (Kimura, Fig. 14).
Kimura (Fig. 14) does not explicitly disclose:
a first wiring electrically connected to the first terminal, passing through an inside of the first resin portion, and extending from the first inner surface side to the first outer surface side in a facing direction in which the first inner surface and the second inner surface face each other, wherein
Kimura (Fig. 12) discloses:
a first wiring (Kimura, wires; Fig. 12, element 4W) electrically connected to the first terminal (Kimura, electrode; Fig. 12, element 12), passing through an inside of the first resin portion, and extending from the first inner surface side (Kimura, Fig. 12, the top side of element 10B can be considered the first inner surface side) to the first outer surface side (Kimura, Fig. 12, the bottom side of element 10B can be considered the first outer surface side) in a facing direction (Kimura, the z-direction can be considered a facing direction) in which the first inner surface and the second inner surface face each other (Kimura, Fig. 12, the bottom side of semiconductor element 10C can be considered the second inner surface),
While Fig. 14 of Kimura does not explicitly disclose the usage of a first wiring electrically connected to the first terminal and the associated configurations, Fig. 12 of Kimura discloses a first wiring electrically connected to the first terminal, passing through an inside of the first resin portion, and extending from the first inner surface side to the first outer surface side in a facing direction in which the first inner surface and the second inner surface face each other. In the absence of any criticality or unexpected results, it would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to utilize the first wiring structure (i.e. attach 4W), as disclosed by Fig. 12 of Kimura, to the Fig. 14 disclosure of Kimura (i.e. the electrode) arriving at the invention as claimed, for the known benefit of providing alternate connections to the various terminals and electrodes within a semiconductor device (¶ Kimura, ¶ [0160]).
Furthermore, Kimura does not explicitly disclose:
the second chip is an optical element having a light receiving portion which receives light incident on the second outer surface or a light emitting portion which generates light emitted from the second outer surface to an outside, and
Shiraishi discloses:
the second chip (Shiraishi, semiconductor element; Fig. 2B, element 107) is an optical element having a light receiving portion which receives light incident on the second outer surface or a light emitting portion which generates light emitted from the second outer surface (Shiraishi, Fig. 2B, the top surface of element 107 can be considered the second outer surface) to an outside (Shiraishi, ¶ [0060], "for example, an LED", as this is an or statement the embodiment where the second chip is a led emitting portion is obtained).
Re: Dependent Claim 6, Kimura and Shiraishi discloses all the limitations of claim 1 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
further comprising:
a third terminal (Kimura, electrodes; Fig. 14, element 14, ¶ [0164], the right instance can be considered a third terminal) of the first chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]) and provided on the first inner surface (Kimura, Fig. 14 shows the electrode, element 14, on the top right side of element 10D, which is the first inner surface); and
a conductive member (Kimura, solder bumps; Fig. 14, element 44) disposed between the first chip and the second chip (Kimura, semiconductor element; Fig. 14, element 10E, ¶ [0165]) to electrically connect the second terminal (Kimura, electrodes; Fig. 14, element 16, ¶ [0165]) and the third terminal (Kimura, ¶ [0165]).
Re: Dependent Claim 7, Kimura and Shiraishi discloses all the limitations of claim 1 on which this claim depends. Kimura (Fig. 14) as modified by Shiraishi, does not explicitly disclose:
a second wiring electrically connected to the second terminal, passing through the inside of the first resin portion, and extending from the first inner surface side to the first outer surface side in the facing direction.
Kimura, Fig. 12 discloses:
a second wiring (Kimura, wires; Fig. 12, element 4W) electrically connected to the second terminal (Kimura, electrode, Fig. 12, element 13) passing through the inside of the first resin portion (Kimura, resin; Fig. 14, element 6, see attached annotated image label 1st resin portion, can be considered a first resin portion), and extending from the first inner surface side to the first outer surface side in the facing direction (Kimura, Fig. 14, z-direction).
While Fig. 14 of Kimura does not explicitly disclose the usage of a second wiring electrically connected to the first terminal and the associated configurations, Fig. 12 of Kimura discloses a second wiring electrically connected to the second terminal, passing through an inside of the first resin portion. In the absence of any criticality or unexpected results, it would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to utilize the first wiring structure (i.e. attach 4W), as disclosed by Fig. 12 of Kimura, to the Fig. 14 disclosure of Kimura (i.e. the electrode of Kimura), arriving at the invention as claimed, for the known benefit of providing alternate connections to the various terminals and electrodes within a semiconductor device (¶ Kimura, ¶ [0160]).
Re: Dependent Claim 8, Kimura and Shiraishi discloses all the limitations of claim 7 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
wherein a width of the first chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]) is smaller than or equal to a width of the second chip (Kimura, semiconductor element; Fig. 14, element 10E, ¶ [0165]) in a width direction (Kimura, Fig. 14, x-direction) orthogonal to the facing direction (Kimura, Fig. 14, z-direction) (Kimura, Fig. 14 shows 10E and 10D have equal "widths" (lengths) along the x-direction, which is orthogonal to the z-direction, which is the facing direction).
Claim(s) 2 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Kimura (US 20200066675 A1) in view of Shiraishi (US 20070015315 A1) and in further view of Park (US 20170110388 A1).
Re: Dependent Claim 2, Kimura and Shiraishi discloses all the limitations of claim 1 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
first chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]), first outer surface (Kimura, Fig. 14, the bottom side of element 10D can be considered a first outer surface);
Kimura, as modified by Shiraishi is silent regarding:
an insulating layer covering the first outer surface of the first chip; and
Park discloses:
an insulating layer (Park, insulating layer; Fig. 1, element 210) covering the first outer surface (Park, second surface; Fig, 1, element 200b) of the first chip (Park, semiconductor chip; Fig. 1, element 200); and
Kimura, as modified by Shiraishi, discloses a first chip and a first outer surface, but does not explicitly disclose an insulating layer covering the first outer surface of the first chip. Park discloses an insulating layer covering the first outer surface of the first chip for use within a semiconductor package. All references disclose semiconductor elements and configurations and are therefore analogous art. It would be obvious to a POSITA before the effective filing date, to include an insulating layer, as disclosed by Park, to the invention of Kimura, as modified by Shiraishi, arriving at the invention as claimed, for the known benefit of preventing electrical shorts between circuit patterns (Park, ¶ [0020]).
Kimura, as modified by Shiraishi and Park further discloses:
a contact portion (Kimura, solder bumps; Fig. 14, element 44) provided to be exposed to an opposite side to the first chip side of the insulating layer, and electrically connected to the first terminal (Kimura, electrodes; Fig. 14, element 14, ¶ [0164 - 0165]).
Claim(s) 3 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Kimura (US 20200066675 A1) in view of Shiraishi (US 20070015315 A1) and in further view of Matsunaga (US 20160114718 A1).
Re: Dependent Claim 3, Kimura and Shiraishi discloses all the limitations of claim 1 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
wherein the second resin portion (Kimura, resin; Fig. 14, element 6, see attached annotated image label 2nd resin portion, can be considered a second resin portion)
Kimura, as modified by Shiraishi, does not explicitly disclose:
wherein the second resin portion is made of a light transmissive resin,
Matsunaga discloses:
light transmissive resin (Matsunaga, light transmissive resin portion; Fig. 2B, element 11).
Kimura, as disclosed by Shiraishi, discloses a second resin portion, but does not explicitly disclose this second resin portion to be made of a light transmissive resin. Matsunaga discloses a method for molding two different resins integrally and a light transmissive resin. All references disclose resin or molding compounds and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to use the light transmissive resin, as disclosed by Matsunaga, in the second resin portion, as disclosed by Kimura and Shiraishi, arriving at the invention as claimed, for the purpose of changing the appearance due to light and/or prevent deterioration (Matsunaga, ¶ [0043]).
Claim(s) 4-5, 9 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kimura (US 20200066675 A1) in view of Shiraishi (US 20070015315 A1) and in further view of Shimizu (US 20120153457 A1).
Re: Dependent Claim 4, Kimura and Shiraishi discloses all the limitations of claim 1 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
wherein the second outer surface (Kimura, Fig. 14, the top side of element 10E can be considered a second outer surface)
Kimura, as modified by Shiraishi, does not explicitly disclose:
wherein the second outer surface is not covered with the second resin portion.
Shimizu discloses:
wherein the second outer surface (Shimizu, top surface of second semiconductor chip; Fig. 25, element 60) is not covered with the second resin portion (Shimizu, resin; Fig. 25, element 62).
Kimura, as modified by Shiraishi, disclose the second outer surface, but does not explicitly disclose that the second outer surface is not covered with the second resin portion. Shimizu discloses that an outer surface is not covered with a resin portion. All references disclose resins and are therefore analogous art. In the absence of any criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to use a tapered resin, as disclosed by Shimizu, for the second resin portion of Kimura, as modified by Shiraishi, arriving at the invention as claimed, for the benefit of securing the semiconductor chip while reducing the overall thickness of the semiconductor package (Shimizu, ¶ [0110] - [0112]).
Re: Dependent Claim 5, Kimura, Shiraishi, and Shimizu discloses all the limitations of claim 4 on which this claim depends. Kimura, as modified by Shiraishi and Shimizu, further discloses:
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wherein the second outer surface (Kimura, Fig. 14, the top side of element 10E can be considered a second outer surface) is positioned closer to the first chip (Kimura, semiconductor element, Fig. 14, element 10D. ¶ [0164]) than a surface of the second resin portion (Kimura, resin; Fig. 14, element 6, see attached annotated image label 2nd resin portion, can be considered a second resin portion) on an opposite side to the first resin portion (Kimura, resin; Fig. 14, element 6, see attached annotated image label 1st resin portion, can be considered a first resin portion) in the facing direction (Kimura, the z-direction can be considered a facing direction) (Kimura, attached annotated Fig. 14 shows that L2, the length associated with a surface of the second resin portion on an opposite side to the first resin portion in the z-direction, is a longer distance than L1, the length from the outer surface to the inner surface of the first chip)
Re: Dependent Claim 9, Kimura and Shiraishi disclose all the limitations of claim 7 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
first chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]), second chip (Kimura, semiconductor element; Fig. 14, element 10E, ¶ [0165])
the first wiring (Kimura, wires; Fig. 12, element 4W) and the second wiring (Kimura, wires; Fig. 12, element 4W) are disposed within a region overlapping the second chip as viewed from the facing direction (Kimura, Fig. 14, z-direction, a region can be drawn enclosing the device of Fig. 14, as modified by Fig. 12 of Kimura, arriving at the invention as claimed)
Kimura, as modified by Shiraishi, does not explicitly disclose:
a width of the first chip is smaller than a width of the second chip in a width direction orthogonal to the facing direction, and
Shimizu discloses:
a width of the first chip (Shimizu, semiconductor chip; Fig. 25, element 20, the length along the left/right direction can be considered a width) is smaller than a width of the second chip (Shimizu, second semiconductor chip; Fig. 25, element 60) in a width direction orthogonal to the facing direction (Shimizu, Fig. 25, the up/down direction can be considered the facing direction, the left/right direction can be considered a width direction orthogonal to the up/down direction), and
Kimura, as modified by Shiraishi, discloses a first chip, a second chip, a first wiring, and second wiring overlapping when viewed from the facing direction. Kimura, as modified by Shiraishi, does not explicitly disclose that a width of the first chip is smaller than a width of the second chip in a width direction orthogonal to the facing direction. Shimizu discloses a width of the first chip is smaller than a width of the second chip in a width direction orthogonal to the facing direction. All disclose semiconductor chips and their configurations and are therefore analogous art. In the absence of criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to change the sizes of the chips, as disclosed by Shimizu, to the device of Kimura, as modified by Shiraishi, arriving at the invention as claimed, as a matter of routine optimization for the predictable result of scaling device size and using less material to form the chip.
Claim(s) 10 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Kimura (US 20200066675 A1) in view of Shiraishi (US 20070015315 A1) and in further view of Kostelnik (US 20160126491 A1).
Re: Dependent Claim 10, Kimura and Shiraishi disclose all the limitations of claim 7 on which this claim depends. Kimura, as modified by Shiraishi, further discloses:
second chip (Kimura, semiconductor element; Fig. 14, element 10E, ¶ [0165]), (Kimura, Fig. 14, the top side of element 10E can be considered a second outer surface), first chip (Kimura, semiconductor element, Fig. 14, element 10D, ¶ [0164]),
Kimura, as modified by Shiraishi, does not explicitly disclose:
wherein the second chip is a first light receiving element having a first light receiving portion that receives light incident on the second outer surface, and
the first chip is a second light receiving element having a second light receiving portion that receives light transmitted through the second chip.
Kostelnik discloses:
light receiving element (Kostelnik, chip; Fig. 1 and Fig. 10, elements 12/12') including an optical element, such as an LED, (Kostelnik, optical element; Fig. 1, element 14, ¶ [0040]), having a first light receiving portion (Kostelnik, optical sensor, not numbered/illustrated; ¶ [0048] "the chip includes an optical sensor for receiving electromagnetic radiation"), that receives light incident on the second outer surface (Kostelnik, Fig. 6 shows light on the outer surface of element 12, which can be an outer surface, ¶ [0060]), and
Kimura, as modified by Shiraishi, disclose a second chip having a second outer surface and a first chip, but do not explicitly disclose wherein the second chip is a first light receiving element having a first light receiving portion that receives light incident on the second outer surface, and the first chip is a second light receiving element having a second light receiving portion that receives light transmitted through the second chip. Kostelnik discloses a chip which includes an integrated LED further comprising an optical sensor used for receiving electromagnetic radiation (light) for use in an optical module (Kostelnik, ¶ [0040]). All references disclose elements of semiconductor devices and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to use the chip disclosed by Kostelnik, for both the first and second chips, as disclosed by Kimura, as modified by Shiraishi, such that both the chips include an LED and an optical sensor (i.e. light receiving portion), for the benefit of using the device for lighting and/or an optical transmitter or receiver for the purpose of signal transmission (Kostelnik, ¶ [0011]). In the absence of criticality or unexpected results, a POSITA would further be motivated to configure the optical components of the stacked chips, as disclosed by Kimura and Shiraishi, such that the light received through the second chip at the outer surface is received by the first chip, arriving at the invention as claimed, as a matter of using optical sensors and LEDS for the known purpose of optical communication between stacked chips.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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