DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190214432 A1; hereinafter Kim) in view of Harari (US 20170148517 A1; hereinafter Harari).
Regarding claim 1, FIG. 3 of Kim teaches a vertical transistor (300 ¶ [0041]), comprising: a source electrode (318 ¶ [0043]); a drain electrode (314, 316 ¶ [0042]-[0043]) disposed above the source electrode (318) and stacked with the source electrode (318); and a gate electrode (302, 310 ¶ [0043]) and a semiconductor layer (306 ¶ [0042]), which are in the same layer (see FIG. 3), and are disposed between the source electrode (318) and the drain electrode (314, 316) in a first direction (y direction) which is perpendicular to the source electrode (318), wherein the gate electrode (302, 310) at least comprises a column-shaped first gate electrode (310) extending in the first direction (y direction ¶ [0043]); and the semiconductor layer (306) comprises a first semiconductor layer (306).
FIG. 3 of Kim does not explicitly teach the source electrode disposed on a substrate; the first direction perpendicular to the substrate.
However, FIG. 4R of Kim teaches a source electrode (424 ¶ [0071]) disposed on a substrate (406 ¶ [0054]); the first direction (y direction) perpendicular to the substrate (406).
Kim does not teach the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.
FIG. 6c of Harari teaches a TFT of a vertical NOR string comprising a first semiconductor layer (656a) and a second semiconductor layer (656b) which are in the same layer and spaced apart from each other (FIG. 6c shows cross-section of TFT with first and second semiconductor layers in same layer and spaced apart by 640 ¶ [0065]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical transistor taught by Kim with the TFT taught by Harari for the purpose of increasing or doubling the read current, enabling the storage of more bits in each memory cell (¶ [0065]).
Thus, Kim in view of teaches the first gate electrode (310 of Kim) disposed between the first semiconductor layer (656a of Harari) and the second semiconductor layer (656b of Harari).
Regarding claim 2, Kim as modified teaches the vertical transistor according to claim 1, and FIG. 3 of Kim further teaches wherein the gate electrode (302, 310) further comprises a second gate electrode (302) which is connected to the first gate electrode (310); and the second gate electrode (302) is disposed around outer side surfaces of the semiconductor layer (306 ¶ [0043]).
Kim does not teach the second gate electrode is disposed around outer side surfaces of the first semiconductor layer and the second semiconductor layer.
However, Kim in view of Harari teaches wherein the second gate electrode (302 of Kim) is disposed around outer side surfaces of the first semiconductor layer (656a of Harari) and the second semiconductor layer (656b of Harari).
Regarding claim 3, Kim as modified teaches the vertical transistor according to claim 1, and FIG. 3 of Kim further teaches wherein the gate electrode (302, 310) further comprises a second gate electrode (302) disposed at an outer side surface of the first semiconductor layer (306 ¶ [0043]).
Regarding claim 4, Kim as modified teaches the vertical transistor according to claim 2 or 3, and FIG. 3 of Kim further teaches wherein both an orthographic projection of the first gate electrode on the substrate (orthographic projection of 310 on 406) and an orthographic projection of the second gate electrode on the substrate (orthographic projection of 302 on 406) are within an orthographic projection of the source electrode (orthographic projection of 318 on 406, see FIG. 3).
Regarding claim 5, Kim as modified teaches the vertical transistor according to claim 4, and FIG. 3 of Kim further teaches wherein the first semiconductor layer (306) has a column-shaped cross-section in a direction which is perpendicular to the substrate (y direction, see FIG. 3).
Regarding claim 6, Kim as modified teaches the vertical transistor according to claim 1, and FIG. 3 of Kim in view of FIG. 6c of Harari further teach wherein both an orthographic projection of the first semiconductor layer (orthographic projection of 656a of Harari) on the substrate (406 of Kim) and an orthographic projection of the second semiconductor layer (orthographic projection of 656b of Harari) on the substrate (406 of Kim) are within an orthographic projection of the source electrode (orthographic projection of 312 of Kim) on the substrate (406 of Kim); and both the orthographic projection of the first semiconductor layer (orthographic projection of 656a of Harari) on the substrate (406 of Kim) and the orthographic projection of the second semiconductor layer (orthographic projection of 656b of Harari) on the substrate (406 of Kim) are within an orthographic projection of the drain electrode (orthographic projection of 314, 316 of Kim) on the substrate (406 of Kim).
Regarding claim 7, Kim as modified teaches the vertical transistor according to claim 1, and FIG. 3 of Kim in view of FIG. 6c of Harari further teach wherein an orthographic projection of the first semiconductor layer (orthographic projection of 656a of Harari) on the substrate (406 of Kim) and an orthographic projection of the second semiconductor layer (orthographic projection of 656b of Harari) on the substrate (406 of Kim) are separated from each other.
Regarding claim 8, Kim as modified teaches the vertical transistor according to claim 1, and FIG. 3 of Kim in view of FIG. 6c of Harari further teach wherein cross-sections of the first semiconductor layer (656a) and the second semiconductor layer (656b) in the first direction (y direction in FIG. 3 of Kim/z direction in FIG. 6c of Harari) are symmetrically distributed about a center line of the gate electrode (310 of Kim).
Allowable Subject Matter
Claims 9-13 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 9 recites a memory cell, comprising: a word line, a bit line, and a vertical transistor, wherein the bit line is disposed at a side, away from a drain electrode, of a source electrode of the vertical transistor, and is connected to the source electrode; the word line is connected to a gate electrode of the vertical transistor; the drain electrode and the source electrode are stacked together, the vertical transistor comprises a semiconductor layer which are in the same layer as the gate electrode, and both the gate electrode and the semiconductor layer are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to a substrate; the gate electrode at least comprises a column-shaped first gate electrode extending in the first direction; the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer; and the bit line comprises a first portion and a second portion which are connected to each other, an orthographic projection of the first portion on the substrate and an orthographic projection of the first semiconductor layer of the vertical transistor on the substrate have an overlapping area, and the orthographic projection of the first portion on the substrate and an orthographic projection of the second semiconductor layer of the vertical transistor on the substrate are separated from each other; and an orthographic projection of the second portion on the substrate and the orthographic projection of the first semiconductor layer on the substrate are separated from each other, and the orthographic projection of the second portion and the orthographic projection of the second semiconductor layer on the substrate have an overlapping area.
FIG. 3 of Kim teaches a vertical transistor comprising a drain electrode, a source electrode, and a gate electrode; the drain electrode and the source electrode are stacked together, the vertical transistor comprises a semiconductor layer which is in the same layer as the gate electrode, and both the gate electrode and the semiconductor layer are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to a substrate; the gate electrode; the gate electrode at least comprises a column-shaped first gate electrode extending in the first direction;
FIG. 6c of Harari teaches a memory cell, comprising: a word line, a bit line, and a vertical transistor, wherein the bit line is disposed at a side, away from the drain electrode, of a source electrode of the vertical transistor, and is connected to the source electrode; the vertical transistor comprises a semiconductor layer; the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other.
Kim in view of Harari teaches the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.
However, the prior art fails to teach or reasonably suggest “the word line is connected to a gate electrode of the vertical transistor… and the bit line comprises a first portion and a second portion which are connected to each other, an orthographic projection of the first portion on the substrate and an orthographic projection of the first semiconductor layer of the vertical transistor on the substrate have an overlapping area, and the orthographic projection of the first portion on the substrate and an orthographic projection of the second semiconductor layer of the vertical transistor on the substrate are separated from each other; and an orthographic projection of the second portion on the substrate and the orthographic projection of the first semiconductor layer on the substrate are separated from each other, and the orthographic projection of the second portion and the orthographic projection of the second semiconductor layer on the substrate have an overlapping area” together with all the limitations of claim 9 as claimed. Claims 10-11 are allowable insofar as they depend upon and require all the limitations of claim 9.
Claim 13 recites a method for manufacturing a memory cell, comprising: forming a first silicon-doped conductive layer, a sacrificial semiconductor layer, and a second silicon-doped conductive layer sequentially at a side of a substrate; forming a plurality of first trenches through a patterning process to distinguish a plurality of transistor row regions, wherein each of the first trenches is flanked by a source row formed by the first silicon-doped conductive layer, a first sacrificial structure row formed by the sacrificial semiconductor layer, and a drain row formed by the second silicon-doped conductive layer which are stacked together; etching back, for each of the transistor row regions, the first sacrificial structure row exposed at a side surface of the first trench to form a sacrificial structure row, wherein sidewalls of the source row, the sacrificial structure row, and the drain row form a U-shaped trench; forming, for each of the transistor row regions, a semiconductor material layer in the U- shaped trench; forming a plurality of second trenches perpendicular to the first trenches on the substrate through the patterning process to distinguish a plurality of transistor regions, wherein each of the transistor regions comprises a source electrode formed by the source row, a semiconductor layer formed by the semiconductor material layer, and a drain electrode formed by the drain row which are stacked together; and a sacrificial structure formed by the sacrificial structure row is in the same layer as the semiconductor layer and is disposed between a first semiconductor layer and a second semiconductor layer comprised in the semiconductor layer; removing the sacrificial structure to form a hole; and adding a conductive material in the hole and on a sidewall of the semiconductor layer through a coating process, and patterning the conductive material to form a gate electrode comprising a first gate electrode and form a word line connected to the first gate electrode.
FIGS. 4A-5 of Kim teach a method for manufacturing a memory cell, comprising: forming a first silicon-doped conductive layer, a sacrificial semiconductor layer, and a second silicon-doped conductive layer sequentially at a side of a substrate; forming a plurality of first trenches through a patterning process to distinguish a plurality of transistor row regions, wherein each of the first trenches is flanked by a source row formed by the first silicon-doped conductive layer, a first sacrificial structure row formed by the sacrificial semiconductor layer, and a drain row formed by the second silicon-doped conductive layer which are stacked together; etching back, for each of the transistor row regions, the first sacrificial structure row exposed at a side surface of the first trench to form a sacrificial structure row; wherein each of the transistor regions comprises a source electrode formed by the source row, a semiconductor layer, and a drain electrode formed by the drain row which are stacked together; and a sacrificial structure formed by the sacrificial structure row is in the same layer as the semiconductor layer; and is disposed between a first portion of the semiconductor layer and a second portion of the semiconductor layer; removing the sacrificial structure to form a hole; and adding a conductive material in the hole and on a sidewall of the semiconductor layer through a coating process, and patterning the conductive material to form a gate electrode comprising a first gate electrode.
FIG. 6c of Harari teaches a memory cell, comprising: a word line, a bit line, and a vertical transistor, wherein the bit line is disposed at a side, away from the drain electrode, of a source electrode of the vertical transistor, and is connected to the source electrode; the vertical transistor comprises a semiconductor layer; the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other.
However, the prior art fails to teach or reasonably suggest “wherein sidewalls of the source row, the sacrificial structure row, and the drain row form a U-shaped trench; forming, for each of the transistor row regions, a semiconductor material layer in the U-shaped trench; forming a plurality of second trenches perpendicular to the first trenches on the substrate through the patterning process to distinguish a plurality of transistor regions” together with all the limitations of claim 13 as claimed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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