DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/30/2024 and 09/26/2025, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Spec does not mention a label for “insulating region” (line 2 of claim 1), formed at a second surface side in a SiC substrate. The insulating film (160) as shown in Fig. 2 is formed on the same surface as the source region “formed on the insulation region along the first surface” as disclosed in claim 1.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “insulating region” (line 2 of claim 1) must be shown and labeled or the feature(s) canceled from the claim(s). No new matter should be entered. It is not clear how the insulating region is separate from the SiC substrate. The drawings, such as is shown in Fig. 2, 6A-6F, and 7 do not clearly show where the insulating region is formed. Is it formed in the substrate (112)? The language of the claim suggests that the insulating region is a separate region. (See line 2 of claim 1). In order to advance prosecution, the Examiner will interpret component (112), labeled as the resistance region, to include the “insulating region” of claim 1 on the semi-insulating substrate (112).
The drawings are also objected to because: the word “source” is misspelled in Fig. 7. The Examiner assumes the word “sourve” labeled as (132) is intended to be “source.”
The drawings are also objected to because based on the language in the specification, Fig. 1 appears to be prior art. [0006] states “FIG. 1 is a diagram showing a typical structure of a silicon-based lateral MOSFET using a pillar structure.” If FIG. 1 is prior art, it must be labeled as “Prior Art”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1-6, 9-10, 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (WO 2016032069) herein referred to as Kim, in view of Matsuda (US 20150295081).
As to claim 1, a SiC semiconductor device comprising
a plurality of semiconductor regions (Fig. 1, plurality of impurity regions, Kim) comprising
an insulation region ([48] Fig. 1, lower electrode 180, Kim) formed at a second surface side in a SiC substrate having a first surface and a second surface ([48] Fig. 1 “lower electrode 180 is provided at a lower end of the SiC substrate”, Kim),
a source region formed on the insulation region along the first surface, a base region, and a drain region ([38] Fig. 1, “semiconductor regions include a source region 130, a drain region 150, and a base region 120 for implementing a FET structure, and between the base region 120 and the drain region 150, Kim), wherein
(Regarding claim(s) 1, Kim does not appear to expressly disclose “the SiC semiconductor device comprises a P/N junction surface extending from the base region toward the drain region on the insulation region” A p-n junction joins a positive (p-type) and negative (n-type) semiconductor creating an internal barrier that only allows electricity to flow in one direction.
Matsuda teaches the semiconductor device comprises a P/N junction surface (21) and (51), extending from the base region (53) toward the drain region (9) [0065]. As disclosed in [0082] of Matsuda, “The P-type embedded layer 51 is disposed beneath the N-type drift region 20, and a PN junction is formed between the drift region 20 and the embedded layer 51. Thus, in the LDMOS transistor in an off state, the drift region 20 can be depleted efficiently... It is possible to improve a drain breakdown voltage (i.e., OFF-BVdss) in the off state. That is, the RESURF effect becomes more effective by the embedded layer 51 present beneath the drift region 20, thereby making it possible to improve OFF-BVdss.”
Matsuda forms “a first auxiliary region of a first conductivity type which is the same conductivity type as the source region” (Matsuda [0065] “an N-type drift layer (N− layer) 21 disposed below the drift region 20” same conductivity type as source region [0065] “N-type source (N+ layer) 7”) and
Matsuda forms “a second auxiliary region of a second conductivity type opposite to the first conductivity type, and parallel to the first surface”. (Matsuda [0065] “P-type embedded layers (P layer) 51 disposed below the drift layer 21” of opposite conductivity type as first conductivity type “ and parallel to the first surface.)
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to replace the source, base and drain region of Kim with the source, base and drain region of Matsuda to form a p-n junction (first auxiliary region and second auxiliary region) for the reasons stated above (obvious).
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As to claim 2, the Kim/Matsuda combination discloses the elements of claim 1 as discussed above and further disclose the SiC semiconductor device of claim 1, wherein
the first auxiliary region (Fig. 1, [0065] N-type drift layer 21, Matsuda) is disposed on the second auxiliary region (Fig. 1, [0065]P-type embedded layer 51, Matsuda).
As to claim 3, the Kim/Matsuda combination discloses the elements of the SiC semiconductor device of claim 1 as discussed above, wherein
the first auxiliary region is disposed beneath the second auxiliary region (Fig. 1 layer 21 directly on layer 51, Matsuda).
As to claim 4, the Kim/Matsuda combination discloses "the SiC semiconductor device of claim 1, as discussed above wherein
The Kim/Matsuda combination does not appear to expressly disclose:
“the doping concentration of the first auxiliary region is lower than the doping concentration of the source region” (Matsuda Fig. 1 shows higher doping N+ for source region than N- region of 1st auxiliary region (21).)
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As to claim 5, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, as discussed above wherein
the doping concentration of the second auxiliary region (P-type concentration 51, second conductivity type, located below the drain; Matsuda) is lower than the doping concentration of the base region (base region 53, Matsuda). See [0088] Thus, the above effect can be obtained because the impurity concentration of the second conductivity type of the first region (below the drain) is lower than the impurity concentration of the second conductivity type of the second region (embedded layer (P).)
As to claim 6, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, as discussed above:
The Kim/Matsuda combination does not appear to expressly disclose “the ratio of the doping concentration of the second auxiliary region to the first auxiliary region is in the range of 0.7 to 1.3.” The 0.7 to 1.3 ratio (obvious) ensures symmetrical electric field distribution and uniform charge carrier flow in semiconductor devices. It ensures both auxiliary regions deplete at the same rate under reverse bias, preventing premature electric field crowding and maximizing the device's voltage-handling capacity.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the ratio of the doping concentration of the second auxiliary region to the first auxiliary region, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that a 0.7 to 1.3 ratio is novel and would not have been found through routine experimentation.
As to claim 9, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, as discussed above wherein
the insulation region has an electrical resistance of 105 Ω-cm or more. (“The insulated or semi-insulated substrate has an electrical resistance of at least 10 .sup.5 Ω-cm.” (BEST MODE Section , paragraph 1, line 2; Kim))
As to claim 10, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, as discussed above wherein
the base region (53, Matsuda) extends between the source region (7, Matsuda) and a current path region to a lower end of the source region (7, Matsuda) to form a junction with the source region (7, Matsuda).
As to claim 12, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 4, but does not appear to expressly disclose ”the dopant concentration of the source and drain regions is 1018 to 1021/cm3.” Designing a balanced dopant concentration ensures the optimal functioning of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the dopant concentration of the source and drain regions is 1018 to 1021/cm3 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that the dopant concentration of the source and drain regions as 1018 to 1021/cm3 is novel and would not have been found through routine experimentation.
As to claim 13, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 4, but does not appear to expressly disclose ”the dopant concentration of the base region is 1*1017 to 5*1017/cm3.“ Designing a balanced dopant concentration (obvious) ensures the optimal functioning of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the dopant concentration of the base region is 1*1017 to 5*1017/cm3since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that the dopant concentration of the base region of 1*1017 to 5*1017/cm3 is novel and would not have been found through routine experimentation.
As to claim 14, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, but does not appear to expressly disclose ”the dopant concentration of the first auxiliary region is 1015/cm3 to 1017/cm3.” Designing a balanced dopant concentration (obvious) ensures the optimal functioning of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the dopant concentration of the first auxiliary region is 1015/cm3 to 1017/cm3since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that the dopant concentration of the first auxiliary region as 1015/cm3 to 1017/cm3 is novel and would not have been found through routine experimentation.
As to claim 15, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, but does not appear to expressly disclose ”the dopant concentration of the second auxiliary region is 1015/cm3 to 1017/cm3.“ Designing a balanced dopant concentration (obvious) ensures the optimal functioning of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the dopant concentration of the second auxiliary region is 1015/cm3 to 1017/cm3since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that the dopant concentration of the second auxiliary region as 1015/cm3 to 1017/cm3 is novel and would not have been found through routine experimentation.
As to claim 16, the Kim/Matsuda combination discloses the SiC semiconductor device of claim 1, wherein
the semiconductor device is a MOSFET or CMOS device. ([34] “The device of FIG. 1 illustrates a metal oxide semiconductor field effect transistor (MOSFET) 100. However, it will be appreciated by those skilled in the art that according to the technical spirit disclosed in the present invention, there are no difficulties in implementing other semiconductor devices such as CMOS devices.” Kim)
As to claim 17, Kim discloses a method for manufacturing a SiC semiconductor device, as discussed above the method comprising:
providing an insulating or semi-insulating SiC substrate ([48] Fig. 1 “lower electrode 180 is provided at a lower end of the SiC substrate”, Kim),;
implanting a dopant into the SiC substrate to form a plurality of semiconductor regions (Fig. 1, plurality of impurity regions, Kim); and
forming electrodes to electrically connect the plurality of doped regions on the SiC substrate, wherein the operation of forming a plurality of semiconductor regions comprises: forming a base region by ion implanting a dopant of a second conductivity type ([38] Fig. 1, “semiconductor regions include a source region 130, a drain region 150, and a base region 120 for implementing a FET structure, and between the base region 120 and the drain region 150, Kim);
(Regarding claim(s) 17, Kim does not appear to expressly disclose “ion implanting a dopant of a first conductivity type and a dopant of the second conductivity type at different ion implantation depths to form a junction structure of a first auxiliary region of the first conductivity type and a second auxiliary region of the second conductivity type (obvious);”
Matsuda teaches the semiconductor device comprising a P/N junction surface (21) and (51), extending from the base region (53) toward the drain region (9) [0065]. As disclosed in [0082] of Matsuda, “The P-type embedded layer 51 is disposed beneath the N-type drift region 20, and a PN junction is formed between the drift region 20 and the embedded layer 51. Thus, in the LDMOS transistor in an off state, the drift region 20 can be depleted efficiently... It is possible to improve a drain breakdown voltage (i.e., OFF-BVdss) in the off state. That is, the RESURF effect becomes more effective by the embedded layer 51 present beneath the drift region 20, thereby making it possible to improve OFF-BVdss.”
Matsuda forms “a first auxiliary region of a first conductivity type which is the same conductivity type as the source region” (Matsuda [0065] “an N-type drift layer (N− layer) 21 disposed below the drift region 20” same conductivity type as source region [0065] “N-type source (N+ layer) 7”) and
Matsuda forms “a second auxiliary region of a second conductivity type opposite to the first conductivity type, and parallel to the first surface”. (Matsuda [0065] “P-type embedded layers (P layer) 51 disposed below the drift layer 21” of opposite conductivity type as first conductivity type “ and parallel to the first surface.)
Matsuda implants: a dopant of the first conductivity type at different ion implantation depths to form a junction structure of a first auxiliary region of the first conductivity type and a second auxiliary region of the second conductivity type”(See Fig. 1 Matsuda) .
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to replace the source, base and drain region of Kim with the source, base and drain regions of Matsuda to form a p-n junction (first auxiliary region and second auxiliary region) for the reasons stated above.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (WO 2016032069) herein referred to as Kim, in view of Matsuda (US 20150295081) and further in view of Liu et al., herein referred to as Liu (US 20150340389)
As to claim 18, the Kim/Matsuda combination discloses the method of claim 17, as discussed above.
However, Kim does not appear to expressly disclose “the source region and the drain region are formed by one ion implantation process.” It is well known in the art to form the source and drain regions using the same ion implantation process (obvious) primarily for symmetry, cost-efficiency, and precise structural alignment.
Liu discloses in [0004] a method “using a mask formed of a material which is used to form the metal layer of a gate, a source and a drain is formed by one ion-implantation process.”
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to form the source region and the drain region of the Kim/Matsuda device by one ion implantation process as in the Liu device because doing both implantations at once ensures identical electrical and physical properties in both regions.
Allowable Subject Matter
Claim(s) 7, 8, 11 and 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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