DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Preliminary Amendment & Claims’ Status
Applicant’s 5/31/2024 preliminary amendment to amend the Specification, Claims, Abstract, and Drawings is acknowledged.
Claims 1-8, 11, 14-17, 20-22, 25-26, and 29-30 are currently pending. Claims 3-8, 11, 14, 16-17, 20-22, 25-26, and 30 have been amended. Claims 9-10, 12-13, 18-19, 23-24, 27-28, and 31-33 have been cancelled. No claims have been newly added.
Claim Objections
Claims 1-8, 11, 14-17, 20-22, 25-26, and 29-30 are objected to because of the following informalities:
Re Claim 1, line 8 refers to “the data line”, where it is unclear which of the data lines of the previously established “a plurality of data lines” in line 5 is being referred to. For purposes of examination, “the data line” in line 8 will be interpreted as “a data line of the plurality of data lines”. Similarly, “the data lines” in line 13 lacks proper antecedent basis, and should be instead, and will be interpreted as”, “the plurality of data lines”.
Re Claim 1, “the transistor” in lines 9 and 19 should be, and will be interpreted as, “each transistor” for proper antecedent basis.
Re Claim 1, “gate group” in line 10 should be “gate line group” for consistency.
Re Claim 1, line 12 refers to “the pixel electrode group”, where it is unclear which of the pixel electrode groups of the previously established “plurality of pixel electrode groups” in line 11 is being referred to. For purposes of examination, “the pixel electrode group” in line 12 will be interpreted as “the plurality of pixel electrode groups”.
Re Claim 1, lines 15-16 refer to “the first common line”, where it is unclear which of the first common lines of the previously established “plurality of first common lines” in line 15 is being referred to. For purposes of examination, “the first common line” in lines 15-16 will be interpreted as “the plurality of first common lines”. Similarly, “the first common line” in lines 17-18 will be interpreted as “the plurality of first common lines”.
Re Claim 2, in line 1 “the pixel electrode” should be, and will be interpreted as, “each pixel electrode” for proper antecedent basis. Similarly, in lines 3 and 6 “the pixel electrode lapping portion” should be, and will be interpreted as, “each pixel electrode lapping portion”. Similarly, in lines 7-8 “at least part of the orthographic projection of the second electrode of the transistor on the substrate” should be, and will be interpreted as, “the at least part of the orthographic projection of the second electrode of each transistor on the substrate”.
Claims 3-4, 7-8, 11, 14-17, 20-22, and 26 contain numerous similar issues (as in using “the” instead of “each” or “each of” or “corresponding”), so further repetition of the same informalities/errors will be avoided to prevent redundancy. Applicant is requested to review all claims to fix errors (mentioned and otherwise) to ensure proper antecedent basis and grammatical correctness.
Re Claim 6, in line 6 “extending” should be “extends” for grammatical correctness.
Re Claim 7, in line 11 “extending” should be “extends” for grammatical correctness. Claim 7 also introduces “a second electrode of the first/second transistor” in lines 8-9, when “a second electrode” was already introduced in Claim 1. For purposes of examination, the “second electrode” in lines 8-9 will be interpreted to be referring to the language introduced in Claim 1.
Re Claim 20, in lines 2-3 “a second sub common trace portion” is interpreted to be “a second sub common line portion” to be consistent with following references to “the second sub common line portion”.
In Re Claims 2-8, 11, 14-17, 20-22, 25-26, and 29-30, they all inherit the objection of Claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-8 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the pixel electrode lapping portion" in lines 1-2 and “the pixel electrode body” in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, Claim 3 will be assumed to be dependent from Claim 2, where said terms were introduced.
Claim 6 recites the limitation “the adjacent pixel electrodes” in line 6. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, Claim 6 will be assumed to be referring to a unique set of adjacent pixel electrodes, unrelated to the adjacent pixel electrodes introduced in Claim 5.
Claims 4-8 and 11 inherit the 112(b) rejection of Claim 3 due to their dependency from Claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, and 14-15 are rejected under U.S.C. 102(a)(1) as being anticipated by Liu (US 2010/0320472 A1).
Re Claim 1, Liu discloses an array substrate (FIG. 4, with reference to FIGS. 5-6; [0024]-[0032]), comprising:
a substrate (38; [0025]);
a plurality of gate line groups (30; [0024]), disposed on a side of the substrate (38) and extending in a first direction (left to right across FIG. 4; [0024]), wherein each gate line group (30) comprises two gate lines (60, 62; [0025]) extending in the first direction (left to right across FIG. 4; [0025]); a plurality of data lines (32; [0024]) extending in a second direction (up and down across FIG. 4; [0024]), wherein the second direction (up and down across FIG. 4) intersects with the first direction (left to right across FIG. 4; [0024]);
a plurality of transistors (26, 28; [0024]), wherein each transistor (26, 28) comprises: a first electrode (66, 68, for transistors 26, 28, respectively; [0026]) electrically connected with the data line (78; [0026]), and a second electrode (70, 72, for transistors 26, 28, respectively; [0026]); wherein a part of an orthographic projection of the second electrode (70, 72, for transistors 26, 28, respectively) of the transistor (26, 28) on the substrate (38; FIG. 6; [0025]) is located between orthographic projections of two gate lines (60, 62) of a same gate group (30) on the substrate (38; FIG. 5; [0025], substrate extends across the device and vertical footprint of the gate lines is clear from FIG. 5);
a plurality of pixel electrode groups (50; [0024]), wherein an orthographic projection of at least a part of the pixel electrode group (50) on the substrate (38; FIG. 6; [0025]) is located in a region (Region A, see FIG. Z1 below) formed due to intersection of the gate line groups (30) and the data lines (32; [0024]); and each pixel electrode group (50) comprises: two pixel electrodes (33, 35; [0025]) distributed in the first direction (left to right across FIG. 4; [0025], at least in part, portions between gate lines 60, 62); and
a plurality of first common lines (36; [0024]), wherein an orthographic projection of the first common line (64; FIG. 6; [0026]) on the substrate (38; [0026]) is located between the orthographic projections of the two gate lines (60, 62) of the same gate line group (30) on the substrate (38; [0026]), and at least part of the orthographic projection of the first common line (64; FIG. 6; [0026]) on the substrate (38) overlaps with at least part of the orthographic projection of the second electrode (70, 72, for transistors 26, 28, respectively) of the transistor (26, 28) on the substrate (38; FIG. 5; [0026]).
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FIG. Z1: Annotated version of FIG. 4 of Liu
Re Claim 2, Liu teaches the array substrate according to Claim 1, while further teaching wherein the pixel electrode (33, 35) comprises a pixel electrode body (33.B, 35.B, see FIG. Z2 below; [0025]) and a pixel electrode lapping portion (33.L, 35.L, see FIG. Z2 below; [0025]) extending from an end of the pixel electrode body (33.B, 35.B; [0025]); wherein a part of an orthographic projection of the pixel electrode lapping portion (33.L, 35.L) on the substrate (38; FIG. 6; [0025]) is located between the orthographic projections of the two gate lines (60, 62) of the same gate line group (30) on the substrate (38; [0025], substrate extends across the device and vertical footprint of the gate lines is clear from FIG. 5); and
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the part of the orthographic projection of the pixel electrode lapping portion (33.L, 35.L) on the substrate (38; FIG. 6; [0025]) overlaps with at least part of the orthographic projection of the second electrode (70, 72, for transistors 26, 28, respectively) of the transistor (26, 28) on the substrate (38; FIG. 6; [0025]).
FIG. Z2: Annotated version of FIG. 5 of Liu
Re Claim 3, Liu teaches the array substrate according to Claim 2, while further teaching wherein the pixel electrode lapping portion (33.L, 35.L) comprises: a first sub-lapping portion (33.L.1, 35.L.1; [0025], see FIG. Z2) extending in the second direction (up and down across FIG. 4; [0025]) and a second sub-lapping portion (33.L.2, 35.L.2; [0025], see FIG. Z2) extending in the first direction (left to right across FIG. 4; [0025]); one end of the first sub-lapping portion (33.L.1, 35.L.1) is electrically connected with the pixel electrode body (33.B, 35.B; [0025]), and the other end of the first sub-lapping portion (33.L.1, 35.L.1) is electrically connected with the second sub-lapping portion (33.L.2, 35.L.2; [0025]); and
an orthographic projection of the second sub-lapping portion on the substrate (33.L.2, 35.L.2; FIG. 6; [0025]) is located between the orthographic projections of the two gate lines (60, 62) of the same gate line group (30) on the substrate (38; [0025], substrate extends across the device and vertical footprint of the gate lines is clear from FIG. 5).
Re Claim 4, Liu teaches the array substrate according to Claim 3, while further teaching wherein the two pixel electrodes (33, 35) of a same pixel electrode group (50) are electrically connected with a same data line (78; [0026]) through the transistor (26, 28; [0026]); and
in the same pixel electrode group (50), second sub-lapping portions (33.L.2, 35.L.2) of the two pixel electrodes (33, 35) extend from corresponding first sub-lapping portions (33.L.1, 35.L.1) towards a side of the same data line (78; [0026]) electrically connected with the two pixel electrodes (33, 35; [0026]).
Re Claim 6, Liu teaches the array substrate according to Claim 3, while further teaching wherein
at least two second sub-lapping portions (33.L.2, 35.L.2) adjacent to each other in the first direction (left to right across FIG. 4; [0025]) have at least parts symmetrical to each other with respect to a first axis (axis along 32; [0025]);
wherein the first axis (axis along 32) is located between the adjacent pixel electrodes (33, 35) and extending in the second direction (up and down across FIG. 4; [0025]).
Re Claim 14, Liu teaches the array substrate according to Claim 2, while further teaching wherein the array substrate comprises:
a first insulating layer (48; [0025]) between a layer (50) where the pixel electrode groups (50) are located ([0025]) and a layer (46) where second electrodes (70, 72, for transistors 26, 28, respectively) of the transistors (26, 28) are located ([0026]); wherein
the first insulating layer (48) comprises first vias (80; [0028]), and the pixel electrode lapping portions (33.L, 35.L) are electrically connected with the second electrodes (70, 72, for transistors 26, 28, respectively) of the transistors (26, 28) through the first vias ([0028], FIG. 6).
Re Claim 15, Liu teaches the array substrate according to Claim 14, while further teaching wherein at least part of an orthographic projection of the first common line (64) on the substrate (38; FIG. 6; [0026]) overlaps with at least part of an orthographic projection of the first via (80) on the substrate (38; FIG. 6; [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Liu, as applied to Claim 2, further in view of Lin et al (US 2019/0286267 A1, hereafter Lin).
Re Claim 20, Liu teaches the array substrate according to Claim 2, while further teaching wherein the first common line (64) comprises: a first sub common line portion (64, portion overlapping 78; [0026]) and a second sub common trace portion (64, portion overlapping 33.L, 35.L; [0026]) arranged in the first direction (left to right across FIG. 4; [0026]); at least part of the first sub common line portion (64, portion overlapping 78) on the substrate (38) overlaps with at least part of the data line (78) on the substrate (38; [0026]); at least part of orthographic projection of the second sub common line portion (64, portion overlapping 33.L, 35.L) on the substrate (38; FIG. 6; [0026]) overlaps with at least part of the orthographic projection of the pixel electrode lapping portion (33.L, 35.L; FIG. 6; [0026]) on the substrate (38; [0026]).
Liu’s embodiment as shown in FIGS. 4-7 do not explicitly disclose orthographic projections of the second sub common line portion (64, portion overlapping 33.L, 35.L) overlapping orthographic projections of the data line (78), as FIGS 6-7 only show sectional views of the first sub common line portion (64, portion overlapping 78). However, since the substrate (38) extends across the device and the vertical footprint of the second sub common line portion (64, portion overlapping 33.L, 35.L) and data line (78) is clear from FIG. 5, the associated limitations with the orthographic projections would be clearly taught when looked upon by one of ordinary skill in the art.
Liu does not explicitly teach wherein a maximum length of the first sub common line portion (64, portion overlapping 78) in the second direction (up and down across FIG. 4) is smaller than a maximum length of the second sub common line portion (64, portion overlapping 33.L, 35.L) in the second direction (up and down across FIG. 4).
However, Lin teaches a substrate (FIG. 2; [0024]) wherein a maximum length of the first sub common line portion (MC2, portion overlapping DL1; [0024]) in the second direction (up and down across FIG. 2) is smaller than a maximum length of the second sub common line portion (MC2, portion not overlapping DL1; [0024]) in the second direction (up and down across FIG. 2; [0024]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate of Liu as discussed with regard to Claim 2 above with the limitations taught by Lin to specifically decrease the width of the portion of the common lines (Liu: 64) intersecting with the data lines (Liu: 78) to reduce the intersection’s capacitance load and improve the display quality as taught by Lin ([0024]).
Claim 30 is rejected under U.S.C. 103 as being unpatentable over Liu, as applied to Claim 1, further in view of Jiang et al (US 2024/0168346 A1, hereafter Jiang).
Re Claim 30, Liu teaches a display panel (FIG. 4; [0024]), comprising the array substrate according to claim 1.
Liu does not explicitly disclose wherein the display panel comprises a counter substrate opposite to the array substrate, wherein the counter substrate is provided with a common electrode layer.
However, Jiang teaches a display panel (FIG. 1; [0058]) comprising a counter substrate (20; [0058]) opposite to the array substrate (10; [0058]), wherein the counter substrate (20) is provided with a common electrode layer (22; [0060]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate of Liu as discussed with regard to Claim 1 above with the limitations taught by Jiang to utilize a counter substrate (Jiang: 20) with a common electrode layer (Jiang: 22) opposite of the array substrate to lower risk of uneven brightness of the edge of the display region as taught by Jiang ([0049]).
Allowable Subject Matter
Claims 5, 7-8, 11, 16-17, 21-22, 25-26, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable (assuming all objections, informalities, and 112 rejections were addressed) if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 5, the prior art cannot anticipate, or render obvious, the limitations of: wherein two second sub-lapping portions of two pixel electrodes adjacent in the second direction extend in opposite directions from the corresponding first sub-lapping portions, in combination with the additionally claimed features of Claim 5.
Re Claim 7, the prior art cannot anticipate, or render obvious, the limitations of: wherein the second axis passes through a center of the pixel electrode and extending in the first direction, in combination with the additionally claimed features of Claim 7.
Re Claim 16, the prior art cannot anticipate, or render obvious, the limitations of: wherein the first insulating layer comprises the color resistor layer, in combination with the additionally claimed features of Claim 16.
Re Claim 21, the prior art cannot anticipate, or render obvious, the limitations of: the second line is disconnected at a position intersecting with the pixel electrode lapping portion, in combination with the additionally claimed features of Claim 21.
In Re Claims 8, 11, Claim 17, and Claims 22, 25-26, 29, they are objected to due to their dependence form Claims 7, 16, and 21, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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