DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “LIGHT DETECTION APPARATUS WITH SEPERATION REGION AND ELECTRONIC DEVICE”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-31 and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PG Pub No US2021/0335862A1).
Regarding claim 21, Lee teaches a light detection apparatus [see figs. 3A-3D, 0041-0042], comprising:
a first pixel (left PX) fig. 3C [0045, 0059] including a first photoelectric conversion region (left PD) fig. 3C [0044] and a first transistor (comprising left 111 impurity regions in left PX) fig. 3C [0060, 0062-0063];
a second pixel (right PX) fig. 3C [0045, 0059] including a second photoelectric conversion region (right PD) fig. 3C [0044] and a second transistor (comprising right 111 impurity regions in right PX) fig. 3C [0060, 0062-0063], wherein the first pixel (left PX) is adjacent to the second pixel (right PX) (in fig. 3C view);
a separation region (region comprising 200) fig. 3C [0045] provided between the first photoelectric conversion region (left PD) and the second photoelectric conversion region (right PD), wherein a part of the separation region (210 of 200) fig. 3C [0047, 0046] extends in a first direction (D2) fig. 3B [0048] in a plan view (see fig. 3B);
a first contact electrode (comprising left 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the first transistor (comprising left 111);
a second contact electrode (comprising right 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the second transistor (comprising right 111 impurity regions in right PX), wherein the first contact electrode (left 370) has a first (non-zero) length in the first direction (D2), and wherein the second contact electrode (right 370) has a second (non-zero) length in the first direction (D2); and
a first conductor (defined as 210 material with CT material) fig. 3C [0047, 0050-0053] (210 doped polysilicon electrically conductive material [0047]; CT electrically conductive metal material [0053]; 210 and CT both physically and electrically connected to each other [0050]) that extends into the separation region (region comprising 200),
wherein first conductor (comprising 210) has a third length (longer than multiple pixels in the first direction (D2)) [see fig. 3B, 0047-0052], and
wherein the third length (210 length in D2 longer than multiple pixels) is longer than the first and second lengths (non-zero length of individual left/right “conductive Plug” 370 disposed in an individual pixel [0067], necessarily having length in D2 less than length on one pixel PX [see fig. 3B] – while 210 is longer than multiple pixels PX; therefore, 210 has a longer length in D2 [see fig. 3A-3B] than an individual left/right contact plug 370 in individual pixel [0067]).
As further evidence that 210 of Lee would necessarily have a longer length in D2 than an individual contact plug 370 of a pixel PX, see also the embodiment of figs. 6A-6B [0104-0105 Lee].
Regarding claim 22, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 21. Lee also teaches further comprising:
a semiconductor layer (100) fig. 3C [0043] in which the first (left PD) fig. 3C [0044] and second (right PD) fig. 3C [0044] photoelectric conversion regions [0044] are disposed.
Regarding claim 23, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 23. Lee also teaches wherein the separation region (region comprising 200) fig. 3C [0045] penetrates through the semiconductor layer (100) fig. 3C [0043].
Regarding claim 24, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 23. Lee also teaches further comprising:
an insulating layer (410) fig. 3C [0049] (such as silicon oxide [0049] - 410 is a “dielectric” layer [0049] separating / insulating the contacts/interconnections, therefore, layer 410 (silicon oxide) [0049] is an insulating layer) on the semiconductor layer (100) fig. 3C [0043], wherein the first conductor (210 with CT material) fig. 3C [0050] (CT portion) penetrates through the insulating layer (410).
Regarding claim 25, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 24. Lee also teaches wherein the first conductor (210 with CT material) fig. 3C [0050] (CT portion), the first contact electrode (left 370) fig. 3C [0067], and the second contact electrode (right 370) fig. 3C [0067] are (directly) on (inner sidewalls of) the insulating layer (410) fig. 3C [0049].
Regarding claim 26, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 24. Lee also teaches wherein the first contact electrode (left 370) fig. 3C [0067] and the second contact electrode (right 370) fig. 3C [0067] penetrate through the insulating layer (410) fig. 3C [0049].
Regarding claim 27, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 26. Lee also teaches wherein, in a cross-sectional view, the first contact electrode (left 370) fig. 3C [0067] and the second contact electrode (right 370) fig. 3C [0067] are separated from one another by the first conductor (middle CT1) and two portions (left/right halves of space comprising middle CT1) fig. 3C [0050] of the separation region (SR) annotated fig. 3C below [0045] (SR defined as region comprising 200 and CT) fig. 3C [0045] (see annotated fig. 3C below).
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Annotated fig. 3C of Lee
Regarding claim 28, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 21. Lee also teaches wherein the first transistor (comprising left 111 impurity regions in left PX) fig. 3C [0060, 0062-0063] and the second transistor (comprising right 111 impurity regions in right PX) fig. 3C [0060, 0062-0063] are amplification transistors (could each correspond to source follower transistors [0062] – source follower transistors amplify potential(s) [0033-0036]).
As further evidence that a “source follower” transistor can be considered as an “amplification” transistor – see [0077-0078] of Suzuki (U.S. PG Pub No US2017/0244919A1) – wherein “amplification transistor SF … forms a source follower” [0078 Suzuki].
Regarding claim 29, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 21. Lee also teaches wherein the first conductor (middle CT) fig. 3C [0050], the first contact electrode (left 370) fig. 3C [0067], and the second contact electrode (right 370) fig. 3C [0067] are at a same level in a cross-sectional view (at same vertical level in fig. 3C; coexist in horizontal plane comprising 410).
Regarding claim 30, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 21. Lee also teaches wherein, in the plan view (when the cross-sectional view of Fig. 3D of the prior art is viewed from the top, i.e., in a plan view, the current limitation is disclosed/anticipated), a line that extends in a second direction (D1), perpendicular to the first direction (D2) [see fig. 3B], passes through the first conductor (210 with CT material) fig. 3C [0050] (CT portion), the first contact electrode (left 370 with respective 470) fig. 3C [0067, 0069], and the second contact electrode (right 370 with respective 470) fig. 3C [0067, 0069] (respective 470-portions of contact electrodes and CT’s coexist in horizontal plane/line stretching in direction D1, shown to be perpendicular to D2 in fig. 3B; the components would necessarily satisfy the claimed positional relationship in D1 in both the explicit cross-sectional view of fig. 3D and an implied, representative plan/top view showing the relative positions of the components in D1).
Regarding claim 31, Lee teaches the light detection apparatus [see figs. 3A-3D, 0041-0042] of claim 21. Lee also teaches wherein the first pixel (left PX) fig. 3C [0045, 0059] comprises a first floating diffusion (left 111) fig. 3C [0060] electrically connected (‘coupled’ [0067]) to the first contact electrode (left 370) fig. 3C [0067], and wherein the second pixel (right PX) fig. 3C [0045, 0059] comprises a second floating diffusion (right 111) fig. 3C [0060] electrically connected (‘coupled’ [0067]) to the second contact electrode (right 370) fig. 3C [0067].
Regarding claim 40, Lee teaches a light detection apparatus [see figs. 3A-3D, 0041-0042], comprising:
a first pixel (left PX) fig. 3C [0045, 0059] including a first photoelectric conversion region (left PD) fig. 3C [0044] and a first transistor (comprising left 111 impurity regions in left PX) fig. 3C [0060, 0062-0063];
a second pixel (right PX) fig. 3C [0045, 0059] including a second photoelectric conversion region (right PD) fig. 3C [0044] and a second transistor (comprising right 111 impurity regions in right PX) fig. 3C [0060, 0062-0063], wherein the first pixel (left PX) is adjacent to the second pixel (right PX) (in fig. 3C view);
a separation region (region comprising 200) fig. 3C [0045] provided between the first photoelectric conversion region (left PD) and the second photoelectric conversion region (right PD), wherein a part of the separation region (210 of 200) fig. 3C [0047, 0046] extends in a first direction (D2) fig. 3B [0048] in a plan view (see fig. 3B);
a first contact electrode (left 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the first transistor (comprising left 111);
a second contact electrode (right 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the second transistor (comprising right 111 impurity regions in right PX), wherein the first contact electrode (left 370) has a first (non-zero) length in the first direction (D2), and wherein the second contact electrode (right 370) has a second (non-zero) length in the first direction (D2); and
a first conductor (defined as 210 material with CT material) fig. 3C [0047, 0050-0053] (210 doped polysilicon electrically conductive material [0047]; CT electrically conductive metal material [0053]; 210 and CT both physically and electrically connected to each other [0050]) that extends (horizontally) between the first contact electrode (left 370) and the second contact electrode (right 370) and into the separation region (region comprising 200),
wherein first conductor (comprising 210) has a third length (longer than multiple pixels in the first direction (D2)) [see fig. 3B, 0047-0052], and wherein the third length (210 length in D2 longer than multiple pixels) is longer than the first and second lengths (non-zero length of individual left/right “conductive Plug” 370 disposed in an individual pixel [0067], necessarily having length in D2 less than length on one pixel PX [see fig. 3B] – while 210 is longer than multiple pixels PX; therefore, 210 has a longer length in D2 [see fig. 3A-3B] than an individual left/right contact plug 370 in individual pixel [0067]).
As further evidence that 210 of Lee would necessarily have a longer length in D2 than an individual contact plug 370 of a pixel PX, see also the embodiment of figs. 6A-6B [0104-0105 Lee].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 32-39 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2021/0335862A1) in view of Hara (U.S. PG Pub No US2019/0115383A1).
Regarding claim 32, Lee teaches an electronic apparatus [see figs. 3A-3D, 0041-0042], comprising:
a light detection apparatus [see figs. 3A-3D, 0041-0042], comprising:
a first pixel (left PX) fig. 3C [0045, 0059] including a first photoelectric conversion region (left PD) fig. 3C [0044] and a first transistor (comprising left 111 impurity regions in left PX) fig. 3C [0060, 0062-0063];
a second pixel (right PX) fig. 3C [0045, 0059] including a second photoelectric conversion region (right PD) fig. 3C [0044] and a second transistor (comprising right 111 impurity regions in right PX) fig. 3C [0060, 0062-0063], wherein the first pixel (left PX) is adjacent to the second pixel (right PX) (in fig. 3C view);
a separation region (region comprising 200) fig. 3C [0045] provided between the first photoelectric conversion region (left PD) and the second photoelectric conversion region (right PD), wherein a part of the separation region (210 of 200) fig. 3C [0047, 0046] extends in a first direction (D2) fig. 3B [0048] in a plan view (see fig. 3B);
a first contact electrode (left 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the first transistor (comprising left 111);
a second contact electrode (right 370) fig. 3C [0067] (formed of same material as contact plug/electrode [0067]) connected to the second transistor (comprising right 111 impurity regions in right PX), wherein the first contact electrode (left 370) has a first (non-zero) length in the first direction (D2), and wherein the second contact electrode (right 370) has a second (non-zero) length in the first direction (D2); and
a first conductor (defined as 210 material with CT material) fig. 3C [0047, 0050-0053] (210 doped polysilicon electrically conductive material [0047]; CT electrically conductive metal material [0053]; 210 and CT both physically and electrically connected to each other [0050]) that extends into the separation region (region comprising 200),
wherein first conductor (comprising 210) has a third length (longer than multiple pixels in the first direction (D2)) [see fig. 3B, 0047-0052], and
wherein the third length (210 length in D2 longer than multiple pixels) is longer than the first and second lengths (non-zero length of individual left/right “conductive Plug” 370 disposed in an individual pixel [0067], necessarily having length in D2 less than length on one pixel PX [see fig. 3B] – while 210 is longer than multiple pixels PX; therefore, 210 has a longer length in D2 [see fig. 3A-3B] than an individual left/right contact plug 370 in individual pixel [0067]).
As further evidence that 210 of Lee would necessarily have a longer length in D2 than an individual contact plug 370 of a pixel PX, see also the embodiment of figs. 6A-6B [0104-0105 Lee].
However, Lee does not explicitly disclose a signal processing circuit; and
a light detection apparatus [see figs. 3A-3D, 0041-0042] (does not explicitly disclose a signal processing circuit separate from light detection apparatus).
Hara teaches an electronic apparatus (EQP) fig. 1A [0014] comprising a signal processing circuit (PRCS) fig. 1A [0015, 0059]; and
a light detection apparatus (APR) fig. 1A [0014] (EQP has signal processing circuit PRCS separate / distinct from photoelectric conversion apparatus APR [0014-0015]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the electronic apparatus of Lee to explicitly comprise the signal processing circuit [0015, 0059] separate from the light detection apparatus [0014] in order to enhance processing support for a variety of signal processing operations [0015-0017, 0059] for signal(s) output from the photodetection apparatus [0059], as taught by Hara.
Regarding claim 33, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 32. Lee also teaches further comprising:
a semiconductor layer (100) fig. 3C [0043] in which the first (left PD) fig. 3C [0044] and second (right PD) fig. 3C [0044] photoelectric conversion regions [0044] are disposed.
Regarding claim 34, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 33. Lee also teaches wherein the separation region (region comprising 200) fig. 3C [0045] penetrates through the semiconductor layer (100) fig. 3C [0043].
Regarding claim 35, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 33. Lee also teaches further comprising:
an insulating layer (410) fig. 3C [0049] (such as silicon oxide [0049] - 410 is a “dielectric” layer [0049] separating / insulating the contacts/interconnections, therefore, layer 410 (silicon oxide) [0049] is an insulating layer) on the semiconductor layer (100) fig. 3C [0043], wherein the first conductor (210 with CT material) fig. 3C [0050] (CT portion) penetrates through the insulating layer (410).
Regarding claim 36, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 35. Lee also teaches further wherein the first conductor (210 with CT material) fig. 3C [0050] (CT portion), the first contact electrode (left 370) fig. 3C [0067], and the second contact electrode (right 370) fig. 3C [0067] are (directly) on (inner sidewalls of) the insulating layer (410) fig. 3C [0049].
Regarding claim 37, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 35. Lee also teaches wherein the first contact electrode (left 370) fig. 3C [0067] and the second contact electrode (right 370) fig. 3C [0067] penetrate through the insulating layer (410) fig. 3C [0049].
Regarding claim 38, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 37. Lee also teaches wherein, in a cross-sectional view, the first contact electrode (left 370) fig. 3C [0067] and the second contact electrode (right 370) fig. 3C [0067] are separated from one another by the first conductor (middle CT1) and two portions (left/right halves of space comprising middle CT1) fig. 3C [0050] of the separation region (SR) annotated fig. 3C below [0045] (SR defined as region comprising 200 and CT) fig. 3C [0045] (see annotated fig. 3C below).
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Annotated fig. 3C of Lee
Regarding claim 39, Lee in view of Hara teaches the electronic apparatus [see figs. 3A-3D, 0041-0042] of claim 32. Lee also teaches wherein the first transistor (comprising left 111 impurity regions in left PX) fig. 3C [0060, 0062-0063] and the second transistor (comprising right 111 impurity regions in right PX) fig. 3C [0060, 0062-0063] are amplification transistors (could each correspond to source follower transistors [0062] – source follower transistors amplify potential(s) [0033-0036]).
As further evidence that a “source follower” transistor can be considered as an “amplification” transistor – see [0077-0078] of Suzuki (U.S. PG Pub No US2017/0244919A1) – wherein “amplification transistor SF … forms a source follower” [0078 Suzuki].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they all feature light-detecting apparatuses with separation region(s) and contact structures.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/25/2026
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