Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 6/3/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Priority
Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged to 371 of PCT/JP2022/045014. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Japanese Unexamined Patent Application Publication No. 2020-88380. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/3/2024 and 6/10/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
TITLE OF THE INVENTION
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LIGHT-RECEIVING DEVICE INCLUDING PLURALITY OF SUBSTRATES COUPLED TO READOUT CIRCUITS.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “element” in claims 1, 6, and 13 is a relative term which renders the claim indefinite. The term “element” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The element could be a photoelectric conversion element or a electrical element such a transistor or a non-electrical element.
For the purposes of examination any electrical element will be considered an “element.”
Claims 1-5, 7-12, and 14-20 are rejected due to their dependence on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryoki et al. US 20190252444 A1 (hereinafter Ryoki).
Regarding claim 1, Ryoki discloses:
A light-receiving device, (Ryoki, 9A, photoelectric semiconductor device.) comprising:
a first substrate (semiconductor layer 11 in chip 1) including a plurality of photoelectric conversion (photoelectric converter 104) sections that photoelectrically converts light;
a second substrate (semiconductor layer 21 in chip 2) including a plurality of readout circuits (See Fig. 9A) that outputs a first signal based on electric charge photoelectrically converted by the photoelectric conversion sections; and ([0060])
a first through-electrode (through-electrodes 251) coupled to each of the readout circuits and penetrating the second substrate, (See Fig. 9A) wherein the first substrate and the second substrate are stacked by bonding (bonding portion 330) between electrodes to allow a first surface of the first substrate on which an element is formed and a second surface of the second substrate on which an element is formed to be opposed to each other, and (See Fig. 9A)
the first through-electrode is provided for each of the readout circuits or for every plurality of readout circuits. (See Fig. 9A)
Regarding claim 2, Ryoki further discloses:
a first wiring layer (first wiring layer 22) provided on a side of the second surface of the second substrate and including wiring lines of two or more layers; and (See Fig.9A)
a second wiring layer (second wiring layer 28) provided on a side of a third surface opposite to the second surface of the second substrate and including wiring lines of three or more layers. (See Fig. 9A)
Regarding claim 3, Ryoki further discloses:
the second wiring layer (second wiring layer 28) includes a wiring line that crosses transversely or longitudinally a region provided with the plurality of readout circuits to reach a peripheral region. (See Fig. 9A, peripheral regions being considered regions at least partially to the side of the photoelectric converter 104)
Regarding claim 4, Ryoki further discloses:
the second wiring layer (second wiring layer 28) includes a wiring line (conductive patterns 2261) including a material same as the first through- electrode. ([0070] through-electrode 251 is made of copper and [0072] conductive patterns are made of copper.)
Regarding claim 5, Ryoki further discloses:
a third substrate (semiconductor layer 31 in chip 3) including a signal processing section that processes the first signal. ([0061], chips 2 and 3 are electrically connected therefore are capable of processing the signal from chip 1. See also [0022], cell 10 includes a photodiode which drives a signal from cell 10 to cells 20 to process said signal.)
Regarding claim 6, Ryoki further discloses:
the second substrate (semiconductor layer 21 in chip 2) and the third substrate (semiconductor layer 31 in chip 3) are stacked by bonding between electrodes (See Fig. 9A)to allow a third surface opposite to the second surface of the second substrate (top surface of semiconductor layer 31 in chip 3) and a fourth surface of the third substrate on which an element is formed to be opposed to each other. (bottom surface of semiconductor layer 31 in chip 3.)
Regarding claim 7, Ryoki further discloses:
the second substrate (semiconductor layer 21 in chip 2) and the third substrate (semiconductor layer 31 in chip 3) are stacked by bonding between electrodes coupled to the first through-electrode. (See Fig. 9A, through-electrodes 251 are electrically coupled to both the semiconductor layer 21 and semiconductor 31.)
Regarding claim 8, Ryoki further discloses:
a third wiring layer (wiring structure 32) provided on a side of the fourth surface of the third substrate, wherein the third wiring layer includes a wiring line (conductive patterns 3241, 3242) that crosses transversely or longitudinally a region provided with the plurality of readout circuits to reach a peripheral region. (See Fig. 9A, peripheral regions being considered regions at least partially to the side of the photoelectric converter 104))
Regarding claim 9, Ryoki further discloses:
a third wiring layer (wiring structure 32) provided on a side of the fourth surface of the third substrate, wherein the third wiring layer (wiring structure 32) is coupled to the first through-electrode (through-electrodes 251) and includes a wiring line(conductive patterns 3241, 3242) that crosses transversely or longitudinally a region provided with the plurality of readout circuits to reach a peripheral region. (See Fig. 9A, through-electrodes 251, 252 are electrically coupled to both the semiconductor layer 21 and semiconductor 31 and peripheral regions being considered regions at least partially to the side of the photoelectric converter 104)))
Regarding claim 17, Ryoki further discloses:
the first through-electrode (through-electrodes 251) is coupled to one of the plurality of readout circuits, or is coupled to each of the plurality of readout circuits. (See Fig. 9A, the through-electrode being at least electrically coupled to the readout circuit.)
Regarding claim 18, Ryoki further discloses:
a plurality of first bonding electrodes provided on a side of the first substrate; (See Fig. 9A, conductive patterns 1241, 1242) and a plurality of second bonding electrodes provided on a side of the second substrate, (See Fig. 9A, conductive patterns 2241, 2242) wherein the first substrate (semiconductor layer 11 in chip 1) and the second substrate (semiconductor layer 21 in chip 2) are stacked by bonding between the plurality of first bonding electrodes and the plurality of second bonding electrodes. (See Fig. 9A)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ryoki as applied to claim 1 above, and further in view of Shohji et al. US 20210104571 A1 (hereinafter Shohji).
Regarding claim 10, Ryoki discloses all the elements of claim 1.
Ryoki does not appear to specifically disclose:
comprising a pad provided on a side of the first surface of the first substrate or on a side opposite to the first surface of the first substrate.
Shohji, which teaches a solid-state imaging device (Shohji, Abstract), discloses:
a pad (Fig. 10A, pad 151) provided on a side of the first surface of the first substrate (on a first surface of the substrate of the first substrate 110A) or on a side opposite to the first surface of the first substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki to have a pad provided on a side of the first surface of the first substrate or on a side opposite to the first surface of the first substrate as taught by Shohji for purposes of an external input/output unit (I/O unit) for exchanging various signals with the outside. (Shohji, [0161].)
Regarding claim 11, Ryoki and Shohji discloses all the elements of claim 10.
Ryoki further discloses:
a second through-electrode (through-electrodes 252) …. and penetrating the second substrate; (See Fig. 9A) and
a second wiring layer (second wiring layer 28) provided on a side of a third surface opposite to the second surface of the second substrate, (See Fig. 9A) wherein the first through-electrode and the second through-electrode have heights different from each other in the second wiring layer. (See Fig. 9A, through-electrode 251 is a different height than through-electrode 252.)
The combination of Ryoki and Shohji would disclose that “a second through-electrode (Ryoki, Fig. 9A, through-electrodes 252) would be electrically “coupled to the pad (Shohji, Fig. 10A, pad 151). The prior art includes each element claimed and each element merely performed the same function as it does separately. One or ordinary skill in the art would have recognized the result of the combination of Ryoki and Shohji were predictable.
Regarding claim 12, Ryoki discloses all the elements of claim 11.
Ryoki further discloses:
the second wiring layer (second wiring layer 28) includes a wiring line (conductive patterns 2261) including a material same as the first through-electrode. ([0070] through-electrode 251 is made of copper and [0072] conductive patterns are made of copper.)
Regarding claim 13, Ryoki discloses all the elements of claim 1.
Ryoki does not appear to specifically disclose:
a third substrate including a signal processing section that processes the first signal; and
a pad provided in the second substrate or on a side of a surface of the third substrate on which an element is formed.
Shohji, which teaches a solid-state imaging device (Shohji, Abstract), discloses:
a third substrate (Shohji, Fig. 10A, third substrate 110C) including a signal processing section that processes the first signal; and ([0162]-[0163], the memory circuit formed in the third substrate 110C, therefore includes a signal processing section.)
a pad (pad 151) provided in the second substrate or on a side of a surface of the third substrate (third substrate 110C) on which an element is formed. (See Fig. 10A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki to have a third substrate including a signal processing section that processes the first signal, and a pad provided in the second substrate or on a side of a surface of the third substrate on which an element is formed as taught by Shohji for purposes of an external input/output unit (I/O unit) for exchanging various signals with the outside. (Shohji, [0161].)
Claims 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryoki as applied to claim 1 above, and further in view of Wang et al. US 20140113398 A1 (hereinafter Wang).
Regarding claim 14, Ryoki discloses all the elements of claim 1.
Ryoki further discloses:
the readout circuit includes an amplification transistor that generates the first signal and a reset transistor, and a plurality of the first through-electrodes
Ryoki does appear to discloses:
a plurality of the first through-electrodes includes at least one of a through- electrode that transmits the first signal, a through-electrode that transmits a signal to control the reset transistor, or a through-electrode coupled to a power supply line.
Wang, which teaches a backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip (Wang, Abstract), discloses:
a plurality of the first through-electrodes (Fig. 3, bonding pads 123 which connects 100A to 100B) includes at least one of a through- electrode that transmits the first signal, (Fig. 1, [0027] fourth transistor in second portion 100B being a selection transistor M4), a through-electrode that transmits a signal to control the reset transistor, ([0027], reset transistor M2) ([0026], The first transistor M1 is coupled to the second portion 100B including selection transistor M4 and reset transistor M2 but the bonding pads.) or a through-electrode coupled to a power supply line. ([0027], the drain of the second and third transistor are coupled to a voltage source VDD.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki to have a plurality of the first through-electrodes includes at least one of a through-electrode that transmits the first signal, a through-electrode that transmits a signal to control the reset transistor, or a through-electrode coupled to a power supply line as taught by Wang for purposes of allowing for electrical signal to pass from one level of a stacked semiconductor structure to another level of the semiconductor structure.
Regarding claim 15, Ryoki discloses all the elements of claim 1.
Ryoki further discloses:
the readout circuit (cell 10) includes an amplification transistor that generates the first signal (detection transistor 103), a selection transistor that outputs the first signal (transfer gate 107), and a reset transistor (reset transistor 102), and a plurality of the first through-electrodes (through-electrodes 251)
Ryoki does not appear to disclose:
a plurality of the first through-electrodes includes at least one of a through- electrode that transmits the first signal, a through-electrode that transmits a signal to control the selection transistor, a through-electrode that transmits a signal to control the reset transistor, or a through-electrode coupled to a power supply line.
Wang, which teaches a backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip (Wang, Abstract), discloses:
a plurality of the first through-electrodes (Fig. 3, bonding pads 123 which connects 100A to 100B) includes at least one of a through- electrode that transmits the first signal (Fig. 1, image sensor 100 includes first portion 100A and 100A, which would transmit the first signal from the photodiode M1), a through-electrode that transmits a signal to control the selection transistor, (Fig. 1, [0027] fourth transistor in second portion 100B being a selection transistor M4) a through-electrode that transmits a signal to control the reset transistor, ([0027], reset transistor M2) ([0026], The first transistor M1 is coupled to the second portion 100B including selection transistor M4 and reset transistor M2 but the bonding pads.) or a through-electrode coupled to a power supply line. ([0027], the drain of the second and third transistor are coupled to a voltage source VDD.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki to have a plurality of the first through-electrodes includes at least one of a through- electrode that transmits the first signal, a through-electrode that transmits a signal to control the selection transistor, a through-electrode that transmits a signal to control the reset transistor, or a through-electrode coupled to a power supply line as taught by Wang for purposes of allowing for electrical signal to pass from one level of a stacked semiconductor structure to another level of the semiconductor structure.
Regarding claim 16, Ryoki and Wang discloses all the elements of claim 15.
Wang further discloses:
wherein the plurality of the first through-electrodes (Fig. 3, bonding pads 123 which connects 100A to 100B ) includes the through-electrode that transmits the first signal, (image sensor 100 includes first portion 100A and 100A, which would transmit the first signal from the photodiode M1) the through-electrode that transmits a signal to control the selection transistor, (Fig. 1, [0027] fourth transistor in second portion 100B being a selection transistor M4) the through-electrode that transmits a signal to control the reset transistor, ([0027], reset transistor M2) ([0026], The first transistor M1 is coupled to the second portion 100B including selection transistor M4 and reset transistor M2 but the bonding pads.) and the through-electrode coupled to the power supply line. ([0026], The first transistor M1 is coupled to the second portion 100B including selection transistor M4 and reset transistor M2 but the bonding pads.)
Regarding claim 19, Ryoki discloses all the elements of claim 1.
Ryoki further discloses:
a second wiring layer (second wiring layer 28) provided on a side of a third surface opposite to the second surface of the second substrate, (See Fig. 19A) wherein
the readout circuit includes an amplification transistor that generates the first signal, a selection transistor that outputs the first signal, and a reset transistor, and
Ryoki does not appear to disclose specifically:
the second wiring layer (Fig. 3, bonding pads 123 which connects 100A to 100B) includes at least one of a wiring line that transmits a signal to control the selection transistor, signal (Fig. 1, [0027] fourth transistor in second portion 100B being a selection transistor M4), a wiring line that transmits a signal to control the reset transistor, ([0027], reset transistor M2) ([0026], The first transistor M1 is coupled to the second portion 100B including selection transistor M4 and reset transistor M2 but the bonding pads.) a wiring line that transmits the first signal, or a power supply line. ([0027], the drain of the second and third transistor are coupled to a voltage source VDD.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki to have the second wiring layer includes at least one of a wiring line that transmits a signal to control the selection transistor, a wiring line that transmits a signal to control the reset transistor, a wiring line that transmits the first signal, or a power supply line as taught by Wang for purposes of allowing for electrical signal to pass from one level of a stacked semiconductor structure to another level of the semiconductor structure.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ryoki and Wang as applied to claim 19 above, and further in view of Togashi US 20160204156 A1 (hereinafter Togashi).
Regarding claim 20, Ryoki and Wang discloses all the elements of claim 19.
Ryoki and Wang does not appear to discloses:
an insulating space is provided around the first through-electrode in the second substrate.
Togashi, which a solid-state imaging device for photoelectric conversion (Togashi, Abstract), discloses:
an insulating space (gap 70) is provided around the first through-electrode (through electrode 50) in the second substrate. (semiconductor substrate 30)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ryoki and Wang to have an insulating space is provided around the first through-electrode in the second substrate as taught by Togashi for purposes of reduce capacitance between the through electrode and the semiconductor substrate. (Togashi, [0072].)
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimotsusa US 20130112849 A1 – Fig 1. A bonding two members (first member 308 and second member 309) which connect a control signal to a peripheral circuit. ([0046].)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights