DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In para-0021, the phrase of “a width of an upper surface of the third metal layer is greater than a width of an upper surface of the third metal layer” is not understood because the phrase is duplicate sentence. Please, revise or delete this para-0021.
Appropriate correction is required.
Claim Objections
Claim 7 is objected to because of the following informalities:
Regarding claim 7, the phrase of “a width of an upper surface of the third metal layer is greater than a width of an upper surface of the third metal layer” is not understood because the phrase is duplicate sentence. Please, revise or cancel the claim 7.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, and 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (U.S. 2020/0144234) in view of Koide (U.S. 2019/0137808).
As to claim 1, Jeon discloses a circuit board (para-0041) as shown in figure 1
and 7, comprising:
a first insulating layer (200) including a cavity (C, para-0042);
a first circuit pattern (510 having bump pads BP) disposed on the first insulating layer (200);
a connection member (22) buried in the cavity (C) of the first insulating layer
(100); and including a pad portion (22a) connected to the first circuit pattern;
a molding layer (30-figure 7, para-0131) buried in the cavity (C) and surrounding the connection member (22),
wherein a width of the molding layer (30) gradually decreases along a direction
from a lower surface to an upper surface of the first insulating layer (200).
Jeon does not specifically disclose the pad portion of the connection member includes: a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer, and wherein a lower surface of the third metal layer includes a first portion in contact with the second metal layer and a second portion not in contact with the second metal layer.
Koide teaches a circuit board (10) comprising the pad portion (PD) including a first metal layer (pd1); a second metal layer (CE) disposed on the first metal layer; and a third metal layer (PE) disposed on the second metal layer (CE), and wherein a lower surface of the third metal layer (PE) includes a first portion (I.e. a central portion) in contact with the second metal layer (CE) and a second portion (the far left or right portions) not in contact with the second metal layer (CE).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Koide employed in the circuit board of Jeon in order to provide excellent bonding and electrical connection structure.
As to claim 2, Jeon as modified by Koide further comprising a post bump (inner via IV) disposed on the first circuit pattern (510); and
a through electrode (400, para-0047) buried in the first insulating layer (200),
overlapped with the connection member (22) in a horizontal direction (figures 5 and 7), and overlapped with the post bump (IV) in a vertical direction;
a first circuit pattern (510) includes a first electrode pattern (bump pad BP) overlapping the connection member (22) in a vertical direction (figure 7) and a second electrode pattern (via pad VP) not overlapping the connection member in the vertical direction,
wherein the pad portion (22a) of the connection member (22, electrode 22a, para-0112) is connected to the first electrode pattern (BP), wherein the post bump (IV) is disposed on the second electrode pattern, and
wherein a width of the through electrode (400) is greater than a width of the pad
portion (22a).
As to claim 3, Jeon as modified by Koide discloses a width of the through electrode (400) changes in the vertical direction, and
wherein the width of the pad portion (22a) is smaller than a width of a region
having a smallest width in an entire region (the region where the portion of the element
400 connected to the element VP) of the through electrode (400).
As to claim 4, Jeon as modified by Koide discloses a width of the first electrode pattern (BP) is smaller than a width of the second electrode pattern (VP).
Regarding claim 6, and as best understood to claim 7, Jeon as modified by Koide teaches a width of the lower surface of the third metal layer (PE) is greater than a width of an upper surface of the second metal layer (CE), para-0051+.
As to claim 16, Jeon as modified by Koide teaches the first metal layer (pd1 includes a first metal material (TiN, Mo, or W), and wherein the second and third metal layers (pd2) include a second metal material (ITO, IZO) different from the first metal material, see para-0051-0052).
As to claim 18, Jeon as modified by Koide teaches the pad portion (PD, see figure 7) includes a lower surface, wherein the lower surface of the pad portion (PD) includes a stepped portion, and wherein the stepped portion is provided at an outer side portion of the lower surface of the pad portion.
Allowable Subject Matter
Claims 8-15, 17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, and 6-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
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/TUAN T DINH/Primary Examiner, Art Unit 2847