Prosecution Insights
Last updated: May 29, 2026
Application No. 18/716,018

SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
Jun 03, 2024
Priority
Dec 01, 2021 — RE 10-2021-0170023 +1 more
Examiner
DINH, TUAN T
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Innotek Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
925 granted / 1174 resolved
+10.8% vs TC avg
Strong +23% interview lift
Without
With
+22.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
24 currently pending
Career history
1209
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
64.6%
+24.6% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1174 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claims are directly to “a circuit board”. Please, revise. The following title is suggested: A CIRCUIT BOARD. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Patil et al. (U.S. 2021/0104467). As to claim 1, Patil discloses a circuit board (200) as shown in figure 2, comprising: a first insulating layer (210) including a cavity (606-figure 6); a connection member (250) buried in the cavity (606) of the first insulating layer (210); and a molding layer (260) buried in the cavity (606) and surrounding the connection member (250), wherein a width of the molding layer (260) gradually decreases along a direction from a lower surface to an upper surface of the first insulating layer (210). Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Jeon et al. (U.S. 2020/0144234) submitted by the applicant. As to claim 1, Jeon discloses a circuit board (para-0041) as shown in figure 1 and 7, comprising: a first insulating layer (300) including a cavity (C, para-0042); a connection member (22) buried in the cavity (C) of the first insulating layer (100); and a molding layer (30-figure 7) buried in the cavity (C) and surrounding the connection member (22), wherein a width of the molding layer (30) gradually decreases along a direction from a lower surface to an upper surface of the first insulating layer (300). As to claim 2, Jeon discloses a first circuit pattern (510) disposed on the first insulating layer (300) and including a first electrode pattern (bump pad BP) overlapping the connection member (22) in a vertical direction (figure 7) and a second electrode pattern (via pad VP) not overlapping the connection member in the vertical direction (figure 7); a post bump (inner via IV) disposed on the second electrode pattern (VP) of the first circuit pattern (510); and a through electrode (400, para-0047) buried in the first insulating layer (300), overlapped with the connection member (22) in a horizontal direction (figure 7), and overlapped with the post bump (IV) in a vertical direction (figure 7); wherein the connection member (22), has a pad portion (electrode 22a, para-0112) connected to the first electrode pattern (BP), and wherein a width of the through electrode (400) is greater than a width of the pad portion (22a). AS to claim 3, Jeon discloses a width of the through electrode (400) changes in the vertical direction, and wherein the width of the pad portion (22a) is smaller than a width of a region having a smallest width in an entire region (the region where the portion of the element 400 connected to the element VP) of the through electrode (400). As to claim 4, Jeon discloses a width of the first electrode pattern (BP) is smaller than a width of the second electrode pattern (VP). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Koh et al. (U.S. 2019/0304914). Regarding claim 18, Jeon discloses a lower surface of the pad portion (22a), except for the pad portion includes a stepped portion, and wherein the stepped portion is provided at an outer side portion of the lower surface of the pad portion. Koh teaches a semiconductor apparatus (105) as shown in figure 1E comprising a connection member (120) having a pad portion (126, 133), the pd portion includes a stepped portion (133), and wherein the stepped portion (133) is provided at an outer side portion of the lower surface of the pad portion. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Koh employed in the circuit board of Jeon in order to provide excellent bonding structure for connecting the connection member to an external element. Allowable Subject Matter Claims 5-17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Jun 03, 2024
Application Filed
Mar 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641727
ELECTRONIC DEVICE
2y 3m to grant Granted May 26, 2026
Patent 12641725
PRINTED CIRCUIT BOARD OVER PRINTED CIRCUIT BOARD ASSEMBLY
2y 5m to grant Granted May 26, 2026
Patent 12635588
SEMICONDUCTOR DEVICE AND CIRCUIT BOARD
2y 8m to grant Granted May 19, 2026
Patent 12628299
STRUCTURE OF ELECTRONIC APPARATUS AND METHOD FOR ASSEMBLING ELECTRONIC APPARATUS
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2y 2m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.9%)
2y 11m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1174 resolved cases by this examiner. Grant probability derived from career allowance rate.

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