Prosecution Insights
Last updated: October 02, 2026
Application No. 18/716,188

POWER SUPPLY MODULE

Non-Final OA §103
Filed
Jun 04, 2024
Priority
Feb 18, 2022 — provisional 63/311,746 +1 more
Examiner
DINH, TUAN T
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
944 granted / 1198 resolved
+18.8% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
1229
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1198 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Note: A voltage regulator board almost always has a ground terminal or pin. Therefore, the ground terminal of the VR board (401) connected to the ground terminal of the second board (422). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 31-36, 38, and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. (U.S. 2021/0385942) cited by the applicant in view of Mori et al. (U.S. Patent 8,208,270). As to claim 31, Wong discloses a power supply module (400a, 400b) as shown in figures 4A-4B comprising: a first substrate (422, para-0032); a control IC (424 or 423), a capacitor (412), an inductor (415), a ground terminal (the left connection receptacle connected to the ground pin 419 of the VR board 401), a voltage input terminal (the right connection receptacle 418 connected to a voltage input 419), [[and a signal transmission substrate]] on a principal surface (top surface of the first substrate 422) of the first substrate; and a submodule (400a) including: a second substrate (VR board/substrate 401) above the inductor (415), the ground and voltage input terminals (418), [[and the signal transmission substrate]]; and fifth to seventh electronic components (102, 103, 105) on a first principal surface (top surface of the second substrate 401) of the second substrate opposite to the first substrate; wherein at least one of the ground terminal (the left 418) and the voltage input terminal (the right 418) extends from the principal surface of the first substrate (422) to a second principal surface of the second substrate (401) facing the first substrate. Wong does not disclose the first substrate including a signal transmission substrate. Mori teaches substrate joining member and three-dimensional structure (40) as shown in figures 1-2 comprising the first substrate (28) including a signal transmission substrate (10). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Mori employed in the power supply module of Wong in order to transmit signal in between the first and second substrates. Regarding claim 32, Wong as modified by Mori discloses the inductor (415, figure 4B) is mounted between the first and second substrates (422, 401) and extends from the principal surface of the first substrate to the second principal surface of the second substrate. Regarding claim 33, Wong as modified by Mori discloses the ground terminal (the ground terminal from the connection receptacle connected to the ground pin 419 of the VR board 401) extends from the principal surface of the first substrate to the second principal surface of the second substrate. Regarding claim 34, Wong as modified by Mori discloses the voltage input terminal (the right connection receptacle 419) extends from the principal surface of the first substrate to the second principal surface of the second substrate (401). Regarding claim 35, Wong as modified by Mori teaches the signal transmission Substrate (10) extends from the principal surface of the first substrate (28) to the second principal surface of the second substrate (37). Regarding claim 36, Wong as modified by Mori discloses the fifth electronic component is a power element (104). Regarding claim 38, Wong as modified by Mori discloses the sixth electronic component is a capacitor (102 or 106). Regarding claim 40, Wong as modified by Mori in figure 5 further comprising one or more additional submodules (500a), and the submodule (500b) and the one or more additional submodules are electrically connected to each other. Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong in view of Mori as applied to claims above, and further in view of Lu et al. (U.S. 2019/0150285). Regarding claim 37, Wong as modified by Mori discloses all the limitations of claimed invention except for a heat sink above the power element. Ganesan teaches input/output package architecture (100) as shown in figure 1a comprising a heat sink (690) above the power element (310, 320) mounted on a substrate (350). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Lu employed in the power supply module of Wong and Mori in order to heat dissipation structure for the power module. Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong in view of Mori as applied to claims above, and further in view of Wang et al. (U.S. Patent 10,129,979). Regarding claim 39, Wong as modified by Mori discloses all of the limitations of claimed invention except for the seventh electronic component is a resistor. Wang teaches a PCB assembly (100) as shown in figure 7 comprising the electronic component is a resistor mounted on the substrate or board. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Wang employed in the power supply module of Wong and Mori in order to limit the flow of electric current and drops voltage level and protect sensitive parts. Allowable Subject Matter Claims 41-60 are allowed. The following is an examiner’s statement of reasons for allowance: Neither the references cited nor the cited references teach, suggest, or in combination of a power supply module having the ground terminal is spaced away from and adjacent to the signal transmission substrate; and the ground terminal is adjacent to the voltage input terminal (claim 41), and first and second submodules, each of the first and second submodules includes: a second substrate; a signal transmission substrate connected between the first substrate and the second substrate; a ground terminal connected between the first substrate and the second substrate; a voltage input terminal connected between the first substrate and the second substrate; a power element on a first principal surface of the second substrate opposite to the first substrate; and an inductor mounted between the first substrate and the second substrate and electrically connected with the power element; wherein each of the ground terminal and the voltage input terminal is provided separately and spaced away from the signal transmission substrate (claim 51). Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Jul 15, 2025
Response after Non-Final Action
Sep 03, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750955
EMBEDDED PACKAGE STRUCTURE, POWER SUPPLY APPARATUS, AND ELECTRONIC DEVICE
3y 0m to grant Granted Sep 29, 2026
Patent 12740147
ELECTRONIC DEVICE
2y 8m to grant Granted Sep 15, 2026
Patent 12733099
ELECTRONICS PACKAGING FOR MOVING PLATFORMS
4y 5m to grant Granted Sep 08, 2026
Patent 12733100
REDUCING PRINTED CIRCUIT BOARD AREA FOR SINGLE-SIDED PRINTED CIRCUIT BOARD
3y 9m to grant Granted Sep 08, 2026
Patent 12727086
FLEXIBLE CIRCUIT BOARD AND METHOD OF MANUFACTURING THEREOF
2y 3m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.1%)
2y 11m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1198 resolved cases by this examiner. Grant probability derived from career allowance rate.

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