DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/4/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING THROUGH-VIA, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC APPARATUS
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kita et al. US PGPub. 2009/0243120. Regarding claim 1, Kita teaches a semiconductor device (fig. 2A-B) [0057], comprising a through-via (3, fig. 2A) [0097] on which a connection electrical conductor (19+11, fig. 2A) [0100]-[0101] is formed via an insulation film (9, fig. 2A) [0101], the through-via (3) being provided on a side wall of a through-hole (1, fig. 2A) [0097] formed in a semiconductor substrate (2, fig. 2A) [0100], wherein the connection electrical conductor (19+11) includes a thin film portion (seed portion 19, fig. 2A) [0101] with a smaller film thickness and a thick film portion (11, fig. 2A) [0100] with a larger film thickness (Kita et al., fig. 2A).
Regarding claim 2, Kita teaches the semiconductor device according to claim 1, wherein a plane (top/plan view) shape of the connection electrical conductor (3) is a shape in which projection portions or depression portions (concavo-convex, fig. 2B) [0097] are provided at one or more positions in a part of a predetermined plane shape (round/circular shape, fig. 2B, [0183]) (Kita et al., fig. 2B).
Regarding claim 3, Kita teaches the semiconductor device according to claim 2, wherein the predetermined plane shape is any one of a circular shape (fig. 2B), an elliptical shape, or a polygonal shape (fig. 11-12) (Kita et al., fig. 2B, [0183]).
Regrading claim 4, Kita teaches the semiconductor device according to claim 3, wherein the predetermined plane shape is the polygonal shape whose corner portions are rounded (fig. 9) (Kita et al., fig. 9, [0183]).
Regarding claim 5, Kita teaches the semiconductor device according to claim 2, wherein the plane shape of the connection electrical conductor (3) is a shape in which the projection portions (concavo-convex, fig. 2B) [0097] are provided at one or more positions outside the predetermined plane shape (Kita et al., fig. 2B).
Regarding claim 7, Kita teaches the semiconductor device according to claim 5, wherein the plane shape of the projection portion is any one of a rectangular shape (fig. 12), a semi-circular shape, a semi-elliptical shape, or a triangular shape (Kita et al., fig. 12, [0183]).
Regarding claim 19, Kita teaches a manufacturing method for a semiconductor device (fig. 2A-B) [0057], comprising forming a connection electrical conductor (19+11, fig. 2A) [0100]-[0101] via an insulation film (9, fig. 2A) [0101] on a side wall of a through-hole (1, fig. 2A) [0097] formed in a semiconductor substrate (2, fig. 2A) [0100] to form a through-via (3, fig. 2A) [0097], wherein the connection electrical conductor (19+11) is formed including a thin film portion (seed portion 19, fig. 2A) [0101] with a smaller film thickness and a thick film portion (11, fig. 2A) [0100]with a larger film thickness (Kita et al., fig. 2A). Regarding claim 20, Kita teaches an electronic apparatus [0134], comprising a semiconductor device (fig. 2A-B) [0057] including a through-via (3, fig. 2A) [0097] on which a connection electrical conductor (19+11, fig. 2A) [0100]-[0101] is formed via an insulation film (9, fig. 2A) [0101] on a side wall of a through-hole (1, fig. 2A) [0097] formed in a semiconductor substrate (2, fig. 2A) [0100], wherein the connection electrical conductor (19+11) includes a thin film portion (seed portion 19, fig. 2A) [0101] with a smaller film thickness and a thick film portion (11, fig. 2A) [0100]with a larger film thickness (Kita et al., fig. 2A).
Allowable Subject Matter
Claims 6 and 8-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “the plane shape of the connection electrical conductor is a shape in which the projection portions are provided at one or more positions inside the predetermined plane shape” as recited in claim 6 in combination with the rest of the limitations of claims 1-2;
a semiconductor device wherein “the plane shape of the projection portion is the rectangular shape whose corner portions are rounded” as recited in claim 8 in combination with the rest of the limitations of claims 1-2, 5 and 7;
a semiconductor device wherein “the connection electrical conductor has a plane shape whose film thickness continuously changes in a circumferential direction” as recited in claim 9 in combination with the rest of the limitations of claim 1;
a semiconductor device wherein “the plane shape of the connection electrical conductor is a shape in which the depression portions are provided at one or more positions inside the predetermined plane shape” as recited in claim 10 in combination with the rest of the limitations of claims 1-2;
a semiconductor device wherein “the plane shape of the connection electrical conductor is a shape in which the projection portions are provided at one or more positions both outside and inside the predetermined plane shape” as recited in claim 11 in combination with the rest of the limitations of claims 1-2;
a semiconductor device wherein “the through-via further includes, on an upper surface of the connection electrical conductor formed on the side wall, a stress suppression film that suppresses stress of the connection electrical conductor” as recited in claim 13 in combination with the rest of the limitations of claim 1;
a semiconductor device wherein “the through-via further includes at least one buffer layer between the connection electrical conductor formed on the side wall and the semiconductor substrate, the at least one buffer layer having a Young's modulus lower than a Young's modulus of the insulation film” as recited in claim 14 in combination with the rest of the limitations of claim 1;
a semiconductor device wherein “the through-via further includes, on a bottom portion of the through-hole, an electrical conductor formed to be thicker than another film formed on the side wall of the through-hole” as recited in claim 15 in combination with the rest of the limitations of claim 1;
a semiconductor device wherein “the connection electrical conductor is connected to a wiring layer closest to the semiconductor substrate inside a multi-layer wiring layer, and an air gap is formed in side surfaces of end portions of the wiring layer in a plane direction and in an upper surface of the wiring layer, the upper surface being located on a side of the semiconductor substrate” as recited in claim 16 in combination with the rest of the limitations of claim 1;
a semiconductor device wherein “the connection electrical conductor is formed, embedded also in a multi-layer wiring layer, and the through-via includes a stack via-hole inside the connection electrical conductor inside the multi-layer wiring layer” as recited in claim 17 in combination with the rest of the limitations of claim 1; and
a semiconductor device wherein “the through-via formed on the semiconductor substrate is set as a first through-via, further comprising a plurality of second through-vias formed on the semiconductor substrate and arranged in a periphery of the first through-via, wherein a second application voltage lower than a first application voltage applied on the first through-via is applied on the second through-via, a second wiring layer electrically connected to a connection electrical conductor of the second through-via is arranged between a first wiring layer to which a connection electrical conductor of the first through-via is directly connected and the semiconductor substrate, and the second wiring layer is configured to not be electrically connected to the first wiring layer” as recited in claim 18 in combination with the rest of the limitations of claim 1.
Claim 12 is also objected to as allowable for further limiting and depending upon allowable claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Koike et al. US PGPub. 2010/0007030 (fig. 2) teaches a semiconductor device with a through-via on which a connection electrical conductor is formed via an insulation film in a through hole of a semiconductor substrate. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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