Prosecution Insights
Last updated: October 01, 2026
Application No. 18/716,457

Manufacturing method of a system in package having several layers and associated manufacturing installation

Non-Final OA §102§103§112
Filed
Jun 13, 2024
Priority
Dec 10, 2021 — FR FR2113285 +1 more
Examiner
NGUYEN, DAO H
Art Unit
Tech Center
Assignee
Thales Group
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1164 granted / 1274 resolved
+31.4% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
39 currently pending
Career history
1294
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
35.8%
-4.2% vs TC avg
§102
54.5%
+14.5% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1274 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the communications dated 06/13/2024. Claims 1-14 are pending in this application. Acknowledges 2. Receipt is acknowledged of the following items from the Applicant. Information Disclosure Statement (IDS) filed on 06/04/2024. The references cited on the PTOL 1449 form have been considered. Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609. Foreign Priority 3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Specification 4. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 5. The following is a quotation of 35 U.S.C. 112: (a) IN GENERAL.— The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. PNG media_image1.png 18 19 media_image1.png Greyscale (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 6. Claim 11 is are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. Claim 11 recites “The method according to claim 1, further comprising optically inspecting.” The claim is indefinite because it is not clear what is optically inspected. Claim Rejections - 35 USC § 102 7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 8. Claims 1-10, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Herrault et al. (US 10,600,739) Regarding claim 1, Herrault discloses a method for manufacturing a system in package having several layers, the method comprising for each current layer: realizing a dielectric substrate 102 by an additive manufacturing technique (see fig. 1, and col. 2, line 40 – col. 3, line 17), the substrate 102 comprising a receiving surface, the receiving surface comprising receiving zones configured to receive electronic components 107, 108; depositing an adhesive (such as µm-bumps 105, 106, or under-bump layers for bonding dies 107, 108 to the substrate 102, see fig. 1; see also col. 10, lines 25-46) in the receiving zones; depositing electronic components 107, 108 in the corresponding receiving zones; depositing interconnecting elements 103 between the electronic components 107, 108; creating at least one interconnection 109 with an adjacent layer; encapsulating the current layer with filler material (encapsulating the dies 107, 108and upper surface of the substrate 102), the filler material forming an outer surface; and preparing the outer surface to receive the next layer (attached to balls 109). Regarding claim 2, Herrault discloses the method according to claim 1, wherein said realizing comprises realizing a polymerization of the dielectric substrate 102. See col. 2, line 64 – col. 3, line 17; col. 10, lines 47-64. Regarding claim 3, Herrault discloses the method according to claim1, wherein the additive manufacturing technique comprises a stereolithography technique or a molten wire deposition technique. See col. 2, lines 64 – col. 3, line 3. Regarding claim 4, Herrault discloses the method according to claim 1,wherein said depositing an adhesive is performed by an endless screw or by a time pressure dispensing system. See col. 2, line 40 – col. 3, line 17; col. 10, lines 25-46. Regarding claim 5, Herrault discloses the method according to claim 1, wherein said depositing electronic components 107, 108 is performed by a deposition head. Regarding claim 6, Herrault discloses the method according to claim 1, further comprising polymerizing the adhesive after said depositing electronic components and before said depositing interconnecting elements. See col. 10, lines 25-46. Regarding claim 7, Herrault discloses the method according to claim 1, wherein said depositing interconnecting elements 103 comprises depositing conductive wires or a conductive ink between the electronic components. See fig. 1. Regarding claim 8, Herrault discloses the method according to claim 1, wherein said creating comprises depositing a conductive adhesive or a plastic loaded with conductive particles. See fig. 1. Regarding claim 9, Herrault discloses the method according to claim 1, wherein said encapsulating comprises filling a volume delimited by the dielectric substrate with the filler material. See fig. 1. Regarding claim 10, Herrault discloses the method according to claim 1, wherein said preparing comprises implementing a stripping technique. See fig. 1. Regarding claim 12, Herrault discloses the manufacturing installation for a system in a multi-layer package, the installation comprising a plurality of modules implementing the method according to claim 1. See col. 1, line 26-41. Regarding claim 13, Herrault discloses the method according to claim 2, wherein said realizing comprises realizing a photopolymerization of the dielectric substrate. See col. 2,l ine 64 – col. 3, line 17. Claim Rejections - 35 U.S.C. § 103 9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Herrault et al. (US 10,600,739) in view of Lin et al. (US 2021/0366889). Regarding claim 14, Herrault discloses the method according to claim 5 comprising all claimed limitations, as discussed above, except for wherein said depositing electronic components 107, 108 further comprises placing heat sinks bonded to the electronic components. Lin discloses a method comprising depositing electronic components 120a, 120b on a substrate INT or 150 (see fig. 7), wherein said depositing electronic components 120a, 120b further comprises placing heat sinks 190 bonded to the electronic components. It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Herrault to further comprise placing heat sink(s) bonded to the electronic components, as that taught by Lin, in order to provide heat dissipation to the system, thereby to increase the performance of the system. Conclusion 11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 August 6, 2026
Read full office action

Prosecution Timeline

Jun 13, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745512
ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS
2y 8m to grant Granted Sep 22, 2026
Patent 12733546
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
3y 2m to grant Granted Sep 08, 2026
Patent 12727139
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
3y 5m to grant Granted Sep 01, 2026
Patent 12720904
METHOD FOR MANUFACTURING DEEP-JUNCTION LOW-GAIN AVALANCHE DETECTORS AND ASSOCIATED SEMICONDUCTOR SUBSTRATES
2y 11m to grant Granted Aug 25, 2026
Patent 12720975
DISPLAY DEVICE AND TILING DISPLAY APPARATUS INCLUDING THE DISPLAY DEVICE
2y 10m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.7%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1274 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month