Prosecution Insights
Last updated: October 25, 2026
Application No. 18/716,459

SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Jun 04, 2024
Priority
Dec 13, 2021 — JP 2021-202008 +1 more
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1072 granted / 1295 resolved
+14.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
1326
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
33.4%
-6.6% vs TC avg
§112
28.8%
-11.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1295 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to an Office action mailed on 06/17/2026 ("06-17-26 OA"), the Applicant (i) substantively amended claims 1, 3, 6, 9-11 and 13, (ii) amended the independent claim 7 to include the limitations of the previously-indicated allowable claim 8 and then canceled claim 8, (iii) added new claims 14-21 and (iv) amended the title on 09/17/2026 (“09-17-26 response”). Currently, claims 1-7 and 9-21 are pending. Response to Arguments Applicant's amendment to the title has overcome the objection to the Specification set forth on page 2 under line item number 1 of the 06-17-26 OA. Applicant's amendment to claim 13 have overcome the 35 U.S.C. 112(b) rejection of claim 13 set forth starting on page 3 under line item number 2 of the 06-17-26 OA. Applicant's amendments to the independent claims 1, 6 and 7 have overcome the prior-art rejections based on ‘215 Tu set forth starting on page 4 under line item numbers 3 and 4 of the 06-17-26 OA. Applicant's amendments to the independent claims 1, 6 and 7 have overcome the prior-art rejections based on ‘862 Tu set forth starting on page 10 under line item numbers 5 and 6 of the 06-17-26 OA. Nevertheless, the substantive amendments to the independent claims 1, 6 and 7 required further consideration and search. New grounds of rejection are provided below. Claim Rejections - 35 USC § 1021 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 4-6 and 16-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2008/0267616 A1 to Kinoshita et al. ("Kinoshita"). Fig. 1 of Kinoshita has been provided and Fig. 7a of Kinoshita has been annotated to support the rejection below: PNG media_image1.png 346 438 media_image1.png Greyscale [AltContent: textbox (EPEP)][AltContent: arrow][AltContent: textbox (S1)][AltContent: arrow][AltContent: textbox (D1)][AltContent: arrow][AltContent: textbox (RP)][AltContent: textbox (S2)][AltContent: arrow] PNG media_image2.png 270 441 media_image2.png Greyscale Regarding independent claim 1, Kinoshita teaches a semiconductor device (see Fig. 7a, for example) comprising: a substrate 21; a semiconductor element 24 (para [0059] - “the solid-state image sensor 24”) that is provided on the substrate 21; a transparent member 26 (para [0055] - “a transparent lid section 26”) that is provided on the semiconductor element 24 through a support part 25 (para [0059] - “an adhesive section 25”); and a sealing resin part 28, 12 (para [0059] - “The sealing section 28 is formed from mold resin.”; para [0081] - “…the lens 11 and the lens holder 12 both made of resin”) that is formed around the semiconductor element 24 and the transparent member 26 on the substrate 21, wherein the sealing resin part 28, 12 has a protrusion part 12 having an upper surface S1 thereof perpendicular to a plate thickness direction D1 of the substrate 21, the upper surface S1 being positioned above a front surface S2 of the transparent member 26 in the plate thickness direction D1, wherein the front surface S2 of the transparent member 26 is exposed and free of a film-like protective material, and wherein the front surface S2 of the transparent member 26 and the sealing resin part 28, 12 form a recess part RP. Regarding claim 4, Kinoshita teaches the protrusion part 12 that has a transparent member covering part extending on the front surface S2 of the transparent member 26 so as to cover an edge part of the front surface of the transparent member 26. Regarding claim 5, Kinoshita teaches a sealing resin receiving part 28 that is provided at an edge part on the front surface S2 of the transparent member 26 and is in contact with the protrusion part 12 on an outer side surface is provided. Regarding independent claim 6, Kinoshita teaches an electronic apparatus 100b (para [0084] - “a camera module 100b”), comprising: a semiconductor device (see Fig. 7a, for example) comprising: a substrate 21; a semiconductor element 24 (para [0059] - “the solid-state image sensor 24”) that is provided on the substrate 21; a transparent member 26 (para [0055] - “a transparent lid section 26”) that is provided on the semiconductor element 24 through a support part 25 (para [0059] - “an adhesive section 25”); and a sealing resin part 28, 12 (para [0059] - “The sealing section 28 is formed from mold resin.”; para [0081] - “…the lens 11 and the lens holder 12 both made of resin”) that is formed around the semiconductor element 24 and the transparent member 26 on the substrate 21, wherein the sealing resin part 28, 12 has a protrusion part 12 having an upper surface S1 thereof perpendicular to a plate thickness direction D1 of the substrate 21, the upper surface S1 being positioned above a front surface S2 of the transparent member 26 in the plate thickness direction D1, wherein the front surface S2 of the transparent member 26 is exposed and free of a film-like protective material, and wherein the front surface S2 of the transparent member 26 and the sealing resin part 28, 12 form a recess part RP includes an exposed peripheral edge part EPEP. Regarding claim 16, Kinoshita teaches the protrusion part 12 that has a transparent member covering part extending on the front surface S2 of the transparent member 26 so as to cover an edge part of the front surface of the transparent member 26. Regarding claim 17, Kinoshita teaches a sealing resin receiving part 28 that is provided at an edge part on the front surface S2 of the transparent member 26 and is in contact with the protrusion part 12 on an outer side surface is provided. Regarding claim 18, Kinoshita teaches the protrusion part 12 that has a substantially constant protrusion height from the front surface S2 of the transparent member 26. Regarding claim 19, Kinoshita teaches the protrusion part 12 that has an inner peripheral-side upper surface part EPEP that is continuous with the front surface S2 of the transparent member 26. Regarding claim 20, Kinoshita teaches the protrusion part 12 that has a substantially constant protrusion height from the front surface S2 of the transparent member 26. Regarding claim 21, Kinoshita teaches the protrusion part 12 that has an inner peripheral-side upper surface part EPEP that is continuous with the front surface S2 of the transparent member 26. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kinoshita. Regarding claims 2 and 14, Kinoshita teaches a general condition of a non-zero dimension between the front surface of the transparent member and the upper surface of the protrusion part in the plate thickness direction. Kinoshita does not disclose a specific condition the dimension being 10 to 200 [Symbol font/0x6D]m. According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Here, Kinoshita teaches said general condition. Unless the Applicant can show that said specific condition produces unexpected results that are different in kind and not different in degree over said general condition taught by Kinoshita, claim 2 and 16 would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, because it would not be inventive to discover the optimum or workable ranges by routine experimentation. The burden shifts to the Applicant to show that the claimed range provides unexpected result that is difference in kind and not difference in degree. See In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Moreover, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04). Since the only difference between the claimed semiconductor device and the semiconductor device taught by Kinoshita is a relative dimension of the dimension being 10 to 200 [Symbol font/0x6D]m, the Court would be more likely than not hold that the claimed semiconductor device is not patentably distinct from the semiconductor device taught by Kinoshita. Also, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify semiconductor device such that the dimension is 10 to 200 [Symbol font/0x6D]m with a reasonable expectation of providing a semiconductor device that is small as possible as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 3 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 3. Independent claim 7 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, wherein the protective material comprises a film-like member that wholly covers the front surface of the transparent member or partially covers the front surface of the transparent member while leaving a peripheral edge part of the front surface uncovered, and a step of removing the protective material is included after the step of forming the sealing resin part. Claims 9-13 are allowed, because they depend from the allowed independent claim 7. Claim 15 is objected to for depending on a rejected base claim 6, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 6 or the base claim 6 is amended to include all of the limitations of claim 15. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 02 October 2026 1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102, §103
Sep 17, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES
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3y 1m to grant Granted Oct 20, 2026
Patent 12772534
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE
3y 0m to grant Granted Oct 20, 2026
Patent 12765395
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
4y 8m to grant Granted Oct 13, 2026
Patent 12765298
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
3y 0m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
93%
With Interview (+10.5%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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