DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-6, is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “by bonding bonding” in claim 1 is used by the claim to mean “bonding two surfaces” while the accepted meaning is “bonding two surfaces refers to the process of joining two or more semiconductor components, substrates, or wafers together to form a single functional unit. This is a critical step in packaging, assembly, and integration of chips, sensors, and other devices.” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claim(s) 1, 5, 7, is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al., US 2015/0064832 A1, in view of Kim et al., US 2017/0154873 A1.
Claim 1. Wan et al., disclose a semiconductor device (such as the one in fig. 3a) comprising:
-two semiconductor layers (items 100/200);
-and a wiring layer (item 114) on one side in a stacking direction and a wiring layer (item 214) on the other side in the stacking direction that are interposed between the semiconductor layers (as seen in fig. 3a), each including a plurality of sets located in an insulating film (item 121/221), the sets each including a connection pad (item 142/242), a wiring line, and a via connecting the connection pad to the wiring line (this limitation would read through [0018] wherein is disclosed Interconnect structure 214 includes a plurality of metal layers in a plurality of dielectric layers (121/221), with metal lines and vias disposed in dielectric layers 221),
-and that are electrically connected to each other by bonding bonding surfaces of the connection pads to each other (this limitation would read through [0019] wherein is disclosed Metal pads 142 are bonded to the respective metal pads 242, so that the devices in wafers 100 and 200 are electrically coupled to each other).
Although, Wan et al., disclose wherein in all the sets in the wiring layer on one side in the stacking direction. Wan appears to not specify the limitation of “a center of the connection pad is located at a first distance from a center of the via in a first direction”.
However, Kim et al., in a similar invention of chip stack structure disclose for example, fig. 2, shows items V1/V2 located between two pads.
To improve solder joint quality and maintain signal integrity, while also complying with manufacturing and design rules. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have a center of the connection pad located at a first distance from a center of the via in a first direction, because in high-frequency or high-density designs, placing the via offset from the pad center can reduce parasitic coupling between adjacent vias and pads, lowering crosstalk and improving impedance control.
Claim 7. Wan et al., disclose a wafer (such as the one in fig. 3a) comprising:
-a laminate including a semiconductor layer (items 100/200: as noted "laminate" refers to a multilayer substrate material) and a wiring layer (item 114/214) stacked on the semiconductor layer;
-and a plurality of chip regions that are arranged in a matrix in plan-view on the laminate, each of the chip regions (item 100’/200’, [0014] including an integrated circuit fabricated therein, wherein the wiring layer includes, for each of the chip regions,
-a plurality of sets that are provided in an insulating film (121/221) and form a part of the integrated circuit, each of the sets including a connection pad (142/242), a wiring line, and a via connecting the connection pad to the wiring line (this limitation would read through [0018] wherein is disclosed Interconnect structure 214 includes a plurality of metal layers in a plurality of dielectric layers (121/221), with metal lines and vias disposed in dielectric layers 121/221).
Although, Wan et al., disclose wherein in all the sets in the wiring layer on one side in the stacking direction. Wan appears to not specify the limitation of “each of the chip regions, a center of the connection pad is at a first distance from a center of the via in a first direction, and the first direction is a direction toward a center or an edge of the laminate in plan-view”.
However, Kim et al., in a similar invention of chip stack structure disclose for example, fig. 2, shows items V1/V2 located between two pads.
To improve solder joint quality and maintain signal integrity, while also complying with manufacturing and design rules. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have a center of the connection pad located at a first distance from a center of the via in a first direction, because in high-frequency or high-density designs, placing the via offset from the pad center can reduce parasitic coupling between adjacent vias and pads, lowering crosstalk and improving impedance control.
Claim 5. The combination of Wan et al., with Kim discloses the semiconductor device according to claim 1, wherein one of the two semiconductor layers includes a photoelectric conversion portion capable of performing photoelectric conversion on incident light (this limitation would read through [0112] of Kim, wherein is disclosed for example, a plurality of transistors transferring and amplifying an electrical signal (e.g., photo charges) corresponding to the incident light may be disposed on a front surface 200a of the second substrate 200 in the backside illuminated image sensor including the unit pixels. In addition, color filters CF and the micro lenses ML for providing the incident light to the photoelectric conversion parts PD may be disposed on the back surface 200b of the second substrate 200.
Allowable Subject Matter
6. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. Claims 2-4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
8. Claim 6 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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